4. Interrupts handling and PLIC
In cheriot-safe interrupts are handled in a hierarchical manner. The CLINT timer and software interrupts directly goes to the processor core as timer interrupt and software interrupt respectively (as defined in MIE CSR). All other interrupts go through PLIC:
- PLIC interrupt #1: TBRE interrupt.
- PLIC interrupt #2: peripheral interrupt (via INTC).
- PLIC interrupt #3: Ethernet MAC interrupt
| Address | Register | R/W | Reset | Description |
|---|---|---|---|---|
| 0x1000_0000 | PRI1 | R/W | 0x0000_0000 | Interrupt source 1 priority |
| 0x1000_0004 | PRI2 | R/W | 0x0000_0000 | Interrupt source 2 priority |
| 0x1000_1000 | Pending | RO | 0x0000_0000 | Interrupt pending bit 0-31 |
| 0x1000_2000 | Enable | R/W | 0x0000_0000 | Enable bits for sources 0-31 |
| 0x1020_0000 | Threshold | R/W | 0x0000_0000 | Priority threshold for context 0 |
| 0x1020_0004 | Claim | R/W | 0x0000_0000 | Claim/Compplete for context 0 |