Cheriot-safe (CHERIoT small and fast FPGA emulator) is an complete FPGA platform for CHERIoT hardware prototyping and embedded software development. It contains a cheriot-ibex core, CHERIoT-enabled risc-v debug modules, TCM memories, an AXI-based internal bus fabric, and a collection of commonly used peripherals.
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In a browser go to: https://github.com/microsoft/cheriot-safe
Click on the purple squigily item in the upper right corner.
Select Settings
Select SSH and GPG keys
Add your SSH key
Authenticate key.
git clone [email protected]:microsoft/cheriot-safe.git <ws>
cd <ws>
git submodule update --init --recursive
See the readme and examples under sim/verilator.
- Review the ./sim/Makefile for the correct path to the vcs simulator.
- Execute: ./trun hello_world
- Test output is in ./out/run/hello_world/...
See the readme under build/
Currently cheriot-safe supports the Diligent Arty A7-100T board.
See the wiki section for more information about the cheri_safe FPGA design