[ImportVerilog] sva prototype #7999
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hailongSun2000
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In #7801 , I trying to find a way to implement SVA in Moore, and firstly I tried to directly translate sva to LTL dialect, but finally I failed, because some feature of SVA is hard to directly translate to LTL, such as property and sequence declare and instantiation, property local variable ...
So I try to firstly translate it in Moore, I just refer to #5310 to implement a draft, and here it is. I use Moore's single-bit type to represent properties, I don't know if it's a the right way.
Besides, I'm still stuck on how to lower some of the implementation to LTL, such as property local variable...