Describe behavior of the HDMA HBlank mode in halt mode (#577)

* Add behavior of the HDMA HBlank mode in halt mode * Add test rom for HDMA HBlank halt behaviour Co-authored-by: Antonio Vivace <[email protected]>
gbdev · Nov 3, 2024 · 01cdc20 · 01cdc20
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commit 01cdc20
Showing 1 changed file with 4 additions and 1 deletion.
diff --git a/src/CGB_Registers.md b/src/CGB_Registers.md
@@ -79,7 +79,10 @@ the program execution continues during the "spaces" between each data
 block. Note that the program should not change the Destination VRAM bank
 (FF4F), or the Source ROM/RAM bank (in case data is transferred from
 bankable memory) until the transfer has completed! (The transfer should
-be paused as described below while the banks are switched)
+be paused as described below while the banks are switched).
+
+Upon halting the CPU (using the [halt instruction](<#Using the HALT Instruction>)),
+the transfer will also be halted and will be resumed only when the CPU resumes execution ([test rom](https://github.com/alloncm/MagenTests?tab=readme-ov-file#vram-dma-hblank-mode) exhibiting this behaviour).
 
 Reading from Register FF55 returns the remaining length (divided by $10,
 minus 1), a value of $FF indicates that the transfer has completed. It