Drop FMA intrinsic #445
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Drop FMA intrinsic #445
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marktwtn
requested changes
Jun 4, 2021
sse2neon.h
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| #if defined(__aarch64__) | ||
| return vreinterpretq_m128_f32(vfmaq_f32(vreinterpretq_f32_m128(a), | ||
| vreinterpretq_f32_m128(mask), | ||
| vreinterpretq_f32_m128(b))); | ||
| #else | ||
| return _mm_add_ps(_mm_mul_ps(b, mask), a); | ||
| #endif |
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Remove the ARM 32-bit implementation since vfmaq_f32 is also supported in A32.
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vfmaq_f32 is only available for VFPv4+. Thus, for Armv7-A targets, we have to take the following cases into consideration:
- VFPv3, which is implemented on Cortex-R4 and R5 processors and the Tegra 2 (Cortex-A9).
- VFPv4, which is implemented on the A15 and Cortex-A7, or later
Reference: https://embeddedartistry.com/blog/2017/10/11/demystifying-arm-floating-point-compiler-options/
Danila Kutenin pointed out: > Technically speaking, _mm_fmadd_ps is not an SSE extension, this was > introduced with fma extension which took place even after AVX. To clarify the purpose of SSE2NEON, this pach would drop the existing FMA implementation. The instruction vfmaq_f32, standing for "fused floating-point multiply-accumulate", is only available for VFPv4+. Thus, for Armv7-A targets, we have to take the following cases into consideration: * VFPv3, which is implemented on Cortex-R4, R5, Cortex-A9 * VFPv4, which is implemented on the A15 and Cortex-A7, or later According to the ACLE spec[1], "__ARM_FEATURE_FMA" is defined to 1 if the hardware floating-point architecture supports fused floating-point multiply-accumulate. Related: #82 [1] https://developer.arm.com/architectures/system-architectures/software-standards/acle
marktwtn
approved these changes
Jun 5, 2021
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Danila Kutenin pointed out:
To clarify the purpose of SSE2NEON, this pach would drop the existing
FMA implementation.
Related: #82