diff --git a/clang/test/CodeGenHLSL/builtins/ByteAddressBuffers-constructors.hlsl b/clang/test/CodeGenHLSL/builtins/ByteAddressBuffers-constructors.hlsl index 45e135427ba9c3..7507e741a9c9ba 100644 --- a/clang/test/CodeGenHLSL/builtins/ByteAddressBuffers-constructors.hlsl +++ b/clang/test/CodeGenHLSL/builtins/ByteAddressBuffers-constructors.hlsl @@ -21,9 +21,9 @@ RasterizerOrderedByteAddressBuffer Buffer2: register(u3, space4); // CHECK: define internal void @_init_resource_bindings() { // CHECK-NEXT: entry: -// CHECK-DXIL-NEXT: %Buffer0_h = call target("dx.RawBuffer", i8, 0, 0) @llvm.dx.handle.fromBinding.tdx.RawBuffer_i8_0_0t(i32 0, i32 0, i32 1, i32 0, i1 false) +// CHECK-DXIL-NEXT: %Buffer0_h = call target("dx.RawBuffer", i8, 0, 0) @llvm.dx.resource.handlefrombinding.tdx.RawBuffer_i8_0_0t(i32 0, i32 0, i32 1, i32 0, i1 false) // CHECK-DXIL-NEXT: store target("dx.RawBuffer", i8, 0, 0) %Buffer0_h, ptr @Buffer0, align 4 -// CHECK-DXIL-NEXT: %Buffer1_h = call target("dx.RawBuffer", i8, 1, 0) @llvm.dx.handle.fromBinding.tdx.RawBuffer_i8_1_0t(i32 2, i32 1, i32 1, i32 0, i1 false) +// CHECK-DXIL-NEXT: %Buffer1_h = call target("dx.RawBuffer", i8, 1, 0) @llvm.dx.resource.handlefrombinding.tdx.RawBuffer_i8_1_0t(i32 2, i32 1, i32 1, i32 0, i1 false) // CHECK-DXIL-NEXT: store target("dx.RawBuffer", i8, 1, 0) %Buffer1_h, ptr @Buffer1, align 4 -// CHECK-DXIL-NEXT: %Buffer2_h = call target("dx.RawBuffer", i8, 1, 1) @llvm.dx.handle.fromBinding.tdx.RawBuffer_i8_1_1t(i32 4, i32 3, i32 1, i32 0, i1 false) +// CHECK-DXIL-NEXT: %Buffer2_h = call target("dx.RawBuffer", i8, 1, 1) @llvm.dx.resource.handlefrombinding.tdx.RawBuffer_i8_1_1t(i32 4, i32 3, i32 1, i32 0, i1 false) // CHECK-DXIL-NEXT: store target("dx.RawBuffer", i8, 1, 1) %Buffer2_h, ptr @Buffer2, align 4 diff --git a/clang/test/CodeGenHLSL/builtins/RWBuffer-constructor-opt.hlsl b/clang/test/CodeGenHLSL/builtins/RWBuffer-constructor-opt.hlsl index d834a22917c1f6..237b97394024c6 100644 --- a/clang/test/CodeGenHLSL/builtins/RWBuffer-constructor-opt.hlsl +++ b/clang/test/CodeGenHLSL/builtins/RWBuffer-constructor-opt.hlsl @@ -11,10 +11,10 @@ void main() { // CHECK: define void @main() // CHECK-NEXT: entry: -// CHECK-SPIRV-NEXT: %Buf_h.i = tail call target("spirv.Image", float, 5, 2, 0, 0, 2, 0) @llvm.spv.handle.fromBinding.tspirv.Image_f32_5_2_0_0_2_0t(i32 3, i32 5, i32 1, i32 0, i1 false) +// CHECK-SPIRV-NEXT: %Buf_h.i = tail call target("spirv.Image", float, 5, 2, 0, 0, 2, 0) @llvm.spv.resource.handlefrombinding.tspirv.Image_f32_5_2_0_0_2_0t(i32 3, i32 5, i32 1, i32 0, i1 false) // CHECK-SPIRV-NEXT: store target("spirv.Image", float, 5, 2, 0, 0, 2, 0) %Buf_h.i, ptr @Buf, align 8 -// CHECK-DXIL-NEXT: %Buf_h.i = tail call target("dx.TypedBuffer", float, 1, 0, 0) @llvm.dx.handle.fromBinding.tdx.TypedBuffer_f32_1_0_0t(i32 3, i32 5, i32 1, i32 0, i1 false) +// CHECK-DXIL-NEXT: %Buf_h.i = tail call target("dx.TypedBuffer", float, 1, 0, 0) @llvm.dx.resource.handlefrombinding.tdx.TypedBuffer_f32_1_0_0t(i32 3, i32 5, i32 1, i32 0, i1 false) // CHECK-DXIL-NEXT: store target("dx.TypedBuffer", float, 1, 0, 0) %Buf_h.i, ptr @Buf, align 4 // CHECK-NEXT: ret void diff --git a/clang/test/CodeGenHLSL/builtins/RWBuffer-constructor.hlsl b/clang/test/CodeGenHLSL/builtins/RWBuffer-constructor.hlsl index c2db56e2b2bddf..e4226abf71b8ec 100644 --- a/clang/test/CodeGenHLSL/builtins/RWBuffer-constructor.hlsl +++ b/clang/test/CodeGenHLSL/builtins/RWBuffer-constructor.hlsl @@ -1,5 +1,5 @@ // RUN: %clang_cc1 -triple dxil-pc-shadermodel6.3-library -x hlsl -emit-llvm -disable-llvm-passes -o - %s | FileCheck %s --check-prefixes=CHECK,CHECK-DXIL -// FIXME: SPIR-V codegen of llvm.spv.handle.fromBinding is not yet implemented +// FIXME: SPIR-V codegen of llvm.spv.resource.handlefrombinding is not yet implemented // RUN-DISABLED: %clang_cc1 -triple spirv-vulkan-library -x hlsl -emit-llvm -disable-llvm-passes -o - %s | FileCheck %s --check-prefixes=CHECK,CHECK-SPIRV // NOTE: SPIRV codegen for resource types is not yet implemented @@ -19,7 +19,7 @@ RWBuffer Buf : register(u5, space3); // CHECK: define internal void @_init_resource_bindings() { // CHECK-NEXT: entry: -// CHECK-DXIL-NEXT: %Buf_h = call target("dx.TypedBuffer", float, 1, 0, 0) @llvm.dx.handle.fromBinding.tdx.TypedBuffer_f32_1_0_0t(i32 3, i32 5, i32 1, i32 0, i1 false) +// CHECK-DXIL-NEXT: %Buf_h = call target("dx.TypedBuffer", float, 1, 0, 0) @llvm.dx.resource.handlefrombinding.tdx.TypedBuffer_f32_1_0_0t(i32 3, i32 5, i32 1, i32 0, i1 false) // CHECK-DXIL-NEXT: store target("dx.TypedBuffer", float, 1, 0, 0) %Buf_h, ptr @Buf, align 4 -// CHECK-SPIRV-NEXT: %Buf_h = call target("dx.TypedBuffer", float, 1, 0, 0) @llvm.spv.handle.fromBinding.tdx.TypedBuffer_f32_1_0_0t(i32 3, i32 5, i32 1, i32 0, i1 false) +// CHECK-SPIRV-NEXT: %Buf_h = call target("dx.TypedBuffer", float, 1, 0, 0) @llvm.spv.resource.handlefrombinding.tdx.TypedBuffer_f32_1_0_0t(i32 3, i32 5, i32 1, i32 0, i1 false) // CHECK-SPIRV-NEXT: store target("dx.TypedBuffer", float, 1, 0, 0) %Buf_h, ptr @Buf, align 4 diff --git a/clang/test/CodeGenHLSL/builtins/StructuredBuffers-constructors.hlsl b/clang/test/CodeGenHLSL/builtins/StructuredBuffers-constructors.hlsl index d84e92242ffb4d..16f4f80231dae4 100644 --- a/clang/test/CodeGenHLSL/builtins/StructuredBuffers-constructors.hlsl +++ b/clang/test/CodeGenHLSL/builtins/StructuredBuffers-constructors.hlsl @@ -37,24 +37,24 @@ RasterizerOrderedStructuredBuffer Buf5 : register(u1, space2); // CHECK: define internal void @_init_resource_bindings() { // CHECK-NEXT: entry: -// CHECK-DXIL-NEXT: %Buf_h = call target("dx.RawBuffer", float, 0, 0) @llvm.dx.handle.fromBinding.tdx.RawBuffer_f32_0_0t(i32 0, i32 10, i32 1, i32 0, i1 false) +// CHECK-DXIL-NEXT: %Buf_h = call target("dx.RawBuffer", float, 0, 0) @llvm.dx.resource.handlefrombinding.tdx.RawBuffer_f32_0_0t(i32 0, i32 10, i32 1, i32 0, i1 false) // CHECK-DXIL-NEXT: store target("dx.RawBuffer", float, 0, 0) %Buf_h, ptr @Buf, align 4 -// CHECK-DXIL-NEXT: %Buf2_h = call target("dx.RawBuffer", float, 1, 0) @llvm.dx.handle.fromBinding.tdx.RawBuffer_f32_1_0t(i32 1, i32 5, i32 1, i32 0, i1 false) +// CHECK-DXIL-NEXT: %Buf2_h = call target("dx.RawBuffer", float, 1, 0) @llvm.dx.resource.handlefrombinding.tdx.RawBuffer_f32_1_0t(i32 1, i32 5, i32 1, i32 0, i1 false) // CHECK-DXIL-NEXT: store target("dx.RawBuffer", float, 1, 0) %Buf2_h, ptr @Buf2, align 4 -// CHECK-DXIL-NEXT: %Buf3_h = call target("dx.RawBuffer", float, 1, 0) @llvm.dx.handle.fromBinding.tdx.RawBuffer_f32_1_0t(i32 0, i32 3, i32 1, i32 0, i1 false) +// CHECK-DXIL-NEXT: %Buf3_h = call target("dx.RawBuffer", float, 1, 0) @llvm.dx.resource.handlefrombinding.tdx.RawBuffer_f32_1_0t(i32 0, i32 3, i32 1, i32 0, i1 false) // CHECK-DXIL-NEXT: store target("dx.RawBuffer", float, 1, 0) %Buf3_h, ptr @Buf3, align 4 -// CHECK-DXIL-NEXT: %Buf4_h = call target("dx.RawBuffer", float, 1, 0) @llvm.dx.handle.fromBinding.tdx.RawBuffer_f32_1_0t(i32 0, i32 4, i32 1, i32 0, i1 false) +// CHECK-DXIL-NEXT: %Buf4_h = call target("dx.RawBuffer", float, 1, 0) @llvm.dx.resource.handlefrombinding.tdx.RawBuffer_f32_1_0t(i32 0, i32 4, i32 1, i32 0, i1 false) // CHECK-DXIL-NEXT: store target("dx.RawBuffer", float, 1, 0) %Buf4_h, ptr @Buf4, align 4 -// CHECK-DXIL-NEXT: %Buf5_h = call target("dx.RawBuffer", float, 1, 1) @llvm.dx.handle.fromBinding.tdx.RawBuffer_f32_1_1t(i32 2, i32 1, i32 1, i32 0, i1 false) +// CHECK-DXIL-NEXT: %Buf5_h = call target("dx.RawBuffer", float, 1, 1) @llvm.dx.resource.handlefrombinding.tdx.RawBuffer_f32_1_1t(i32 2, i32 1, i32 1, i32 0, i1 false) // CHECK-DXIL-NEXT: store target("dx.RawBuffer", float, 1, 1) %Buf5_h, ptr @Buf5, align 4 -// CHECK-SPIRV-NEXT: %Buf_h = call target("dx.RawBuffer", float, 0, 0) @llvm.spv.handle.fromBinding.tdx.RawBuffer_f32_0_0t(i32 0, i32 10, i32 1, i32 0, i1 false) +// CHECK-SPIRV-NEXT: %Buf_h = call target("dx.RawBuffer", float, 0, 0) @llvm.spv.resource.handlefrombinding.tdx.RawBuffer_f32_0_0t(i32 0, i32 10, i32 1, i32 0, i1 false) // CHECK-SPIRV-NEXT: store target("dx.RawBuffer", float, 0, 0) %Buf_h, ptr @Buf", align 4 -// CHECK-SPIRV-NEXT: %Buf2_h = call target("dx.RawBuffer", float, 1, 0) @llvm.spv.handle.fromBinding.tdx.RawBuffer_f32_1_0t(i32 1, i32 5, i32 1, i32 0, i1 false) +// CHECK-SPIRV-NEXT: %Buf2_h = call target("dx.RawBuffer", float, 1, 0) @llvm.spv.resource.handlefrombinding.tdx.RawBuffer_f32_1_0t(i32 1, i32 5, i32 1, i32 0, i1 false) // CHECK-SPIRV-NEXT: store target("dx.RawBuffer", float, 1, 0) %Buf2_h, ptr @Buf2", align 4 -// CHECK-SPIRV-NEXT: %Buf3_h = call target("dx.RawBuffer", float, 0, 0) @llvm.spv.handle.fromBinding.tdx.RawBuffer_f32_1_0t(i32 0, i32 3, i32 1, i32 0, i1 false) +// CHECK-SPIRV-NEXT: %Buf3_h = call target("dx.RawBuffer", float, 0, 0) @llvm.spv.resource.handlefrombinding.tdx.RawBuffer_f32_1_0t(i32 0, i32 3, i32 1, i32 0, i1 false) // CHECK-SPIRV-NEXT: store target("dx.RawBuffer", float, 0, 0) %Buf3_h, ptr @Buf3, align 4 -// CHECK-SPIRV-NEXT: %Buf4_h = call target("dx.RawBuffer", float, 1, 0) @llvm.spv.handle.fromBinding.tdx.RawBuffer_f32_1_0t(i32 0, i32 4, i32 1, i32 0, i1 false) +// CHECK-SPIRV-NEXT: %Buf4_h = call target("dx.RawBuffer", float, 1, 0) @llvm.spv.resource.handlefrombinding.tdx.RawBuffer_f32_1_0t(i32 0, i32 4, i32 1, i32 0, i1 false) // CHECK-SPIRV-NEXT: store target("dx.RawBuffer", float, 1, 0) %Buf4_h, ptr @Buf4, align 4 -// CHECK-SPIRV-NEXT: %Buf5_h = call target("dx.RawBuffer", float, 1, 1) @llvm.spv.handle.fromBinding.tdx.RawBuffer_f32_1_1t(i32 2, i32 1, i32 1, i32 0, i1 false) +// CHECK-SPIRV-NEXT: %Buf5_h = call target("dx.RawBuffer", float, 1, 1) @llvm.spv.resource.handlefrombinding.tdx.RawBuffer_f32_1_1t(i32 2, i32 1, i32 1, i32 0, i1 false) // CHECK-SPIRV-NEXT: store target("dx.RawBuffer", float, 1, 1) %Buf5_h, ptr @Buf5, align 4 diff --git a/clang/test/CodeGenHLSL/builtins/StructuredBuffers-methods-lib.hlsl b/clang/test/CodeGenHLSL/builtins/StructuredBuffers-methods-lib.hlsl index 53abdc71bdd4b8..5fc2d2ead564d4 100644 --- a/clang/test/CodeGenHLSL/builtins/StructuredBuffers-methods-lib.hlsl +++ b/clang/test/CodeGenHLSL/builtins/StructuredBuffers-methods-lib.hlsl @@ -15,14 +15,14 @@ export int TestIncrementCounter() { } // CHECK: define noundef i32 @_Z20TestIncrementCounterv() -// CHECK-DXIL: %[[INDEX:.*]] = call i32 @llvm.dx.bufferUpdateCounter.tdx.RawBuffer_f32_1_0t(target("dx.RawBuffer", float, 1, 0) %{{[0-9]+}}, i8 1) +// CHECK-DXIL: %[[INDEX:.*]] = call i32 @llvm.dx.resource.updatecounter.tdx.RawBuffer_f32_1_0t(target("dx.RawBuffer", float, 1, 0) %{{[0-9]+}}, i8 1) // CHECK-DXIL: ret i32 %[[INDEX]] export int TestDecrementCounter() { return RWSB2.DecrementCounter(); } // CHECK: define noundef i32 @_Z20TestDecrementCounterv() -// CHECK-DXIL: %[[INDEX:.*]] = call i32 @llvm.dx.bufferUpdateCounter.tdx.RawBuffer_f32_1_0t(target("dx.RawBuffer", float, 1, 0) %{{[0-9]+}}, i8 -1) +// CHECK-DXIL: %[[INDEX:.*]] = call i32 @llvm.dx.resource.updatecounter.tdx.RawBuffer_f32_1_0t(target("dx.RawBuffer", float, 1, 0) %{{[0-9]+}}, i8 -1) // CHECK-DXIL: ret i32 %[[INDEX]] export void TestAppend(float value) { @@ -31,7 +31,7 @@ export void TestAppend(float value) { // CHECK: define void @_Z10TestAppendf(float noundef %value) // CHECK-DXIL: %[[VALUE:.*]] = load float, ptr %value.addr, align 4 -// CHECK-DXIL: %[[INDEX:.*]] = call i32 @llvm.dx.bufferUpdateCounter.tdx.RawBuffer_f32_1_0t(target("dx.RawBuffer", float, 1, 0) %{{[0-9]+}}, i8 1) +// CHECK-DXIL: %[[INDEX:.*]] = call i32 @llvm.dx.resource.updatecounter.tdx.RawBuffer_f32_1_0t(target("dx.RawBuffer", float, 1, 0) %{{[0-9]+}}, i8 1) // CHECK-DXIL: %[[RESPTR:.*]] = call ptr @llvm.dx.resource.getpointer.p0.tdx.RawBuffer_f32_1_0t(target("dx.RawBuffer", float, 1, 0) %{{[0-9]+}}, i32 %[[INDEX]]) // CHECK-DXIL: store float %[[VALUE]], ptr %[[RESPTR]], align 4 @@ -40,10 +40,10 @@ export float TestConsume() { } // CHECK: define noundef float @_Z11TestConsumev() -// CHECK-DXIL: %[[INDEX:.*]] = call i32 @llvm.dx.bufferUpdateCounter.tdx.RawBuffer_f32_1_0t(target("dx.RawBuffer", float, 1, 0) %1, i8 -1) +// CHECK-DXIL: %[[INDEX:.*]] = call i32 @llvm.dx.resource.updatecounter.tdx.RawBuffer_f32_1_0t(target("dx.RawBuffer", float, 1, 0) %1, i8 -1) // CHECK-DXIL: %[[RESPTR:.*]] = call ptr @llvm.dx.resource.getpointer.p0.tdx.RawBuffer_f32_1_0t(target("dx.RawBuffer", float, 1, 0) %0, i32 %[[INDEX]]) // CHECK-DXIL: %[[VALUE:.*]] = load float, ptr %[[RESPTR]], align 4 // CHECK-DXIL: ret float %[[VALUE]] -// CHECK: declare i32 @llvm.dx.bufferUpdateCounter.tdx.RawBuffer_f32_1_0t(target("dx.RawBuffer", float, 1, 0), i8) +// CHECK: declare i32 @llvm.dx.resource.updatecounter.tdx.RawBuffer_f32_1_0t(target("dx.RawBuffer", float, 1, 0), i8) // CHECK: declare ptr @llvm.dx.resource.getpointer.p0.tdx.RawBuffer_f32_1_0t(target("dx.RawBuffer", float, 1, 0), i32) diff --git a/clang/test/CodeGenHLSL/builtins/StructuredBuffers-methods-ps.hlsl b/clang/test/CodeGenHLSL/builtins/StructuredBuffers-methods-ps.hlsl index f6959b5cefb7cd..f7c091084d3edd 100644 --- a/clang/test/CodeGenHLSL/builtins/StructuredBuffers-methods-ps.hlsl +++ b/clang/test/CodeGenHLSL/builtins/StructuredBuffers-methods-ps.hlsl @@ -10,19 +10,19 @@ RasterizerOrderedStructuredBuffer ROSB1, ROSB2; export void TestIncrementCounter() { // CHECK: define void @_Z20TestIncrementCounterv() -// CHECK-DXIL: call i32 @llvm.dx.bufferUpdateCounter.tdx.RawBuffer_f32_1_0t(target("dx.RawBuffer", float, 1, 0) %{{[0-9]+}}, i8 1) -// CHECK-DXIL: call i32 @llvm.dx.bufferUpdateCounter.tdx.RawBuffer_f32_1_1t(target("dx.RawBuffer", float, 1, 1) %{{[0-9]+}}, i8 1) +// CHECK-DXIL: call i32 @llvm.dx.resource.updatecounter.tdx.RawBuffer_f32_1_0t(target("dx.RawBuffer", float, 1, 0) %{{[0-9]+}}, i8 1) +// CHECK-DXIL: call i32 @llvm.dx.resource.updatecounter.tdx.RawBuffer_f32_1_1t(target("dx.RawBuffer", float, 1, 1) %{{[0-9]+}}, i8 1) RWSB1.IncrementCounter(); ROSB1.IncrementCounter(); } export void TestDecrementCounter() { // CHECK: define void @_Z20TestDecrementCounterv() -// CHECK-DXIL: call i32 @llvm.dx.bufferUpdateCounter.tdx.RawBuffer_f32_1_0t(target("dx.RawBuffer", float, 1, 0) %{{[0-9]+}}, i8 -1) -// CHECK-DXIL: call i32 @llvm.dx.bufferUpdateCounter.tdx.RawBuffer_f32_1_1t(target("dx.RawBuffer", float, 1, 1) %{{[0-9]+}}, i8 -1) +// CHECK-DXIL: call i32 @llvm.dx.resource.updatecounter.tdx.RawBuffer_f32_1_0t(target("dx.RawBuffer", float, 1, 0) %{{[0-9]+}}, i8 -1) +// CHECK-DXIL: call i32 @llvm.dx.resource.updatecounter.tdx.RawBuffer_f32_1_1t(target("dx.RawBuffer", float, 1, 1) %{{[0-9]+}}, i8 -1) RWSB2.DecrementCounter(); ROSB2.DecrementCounter(); } -// CHECK: declare i32 @llvm.dx.bufferUpdateCounter.tdx.RawBuffer_f32_1_0t(target("dx.RawBuffer", float, 1, 0), i8) -// CHECK: declare i32 @llvm.dx.bufferUpdateCounter.tdx.RawBuffer_f32_1_1t(target("dx.RawBuffer", float, 1, 1), i8) +// CHECK: declare i32 @llvm.dx.resource.updatecounter.tdx.RawBuffer_f32_1_0t(target("dx.RawBuffer", float, 1, 0), i8) +// CHECK: declare i32 @llvm.dx.resource.updatecounter.tdx.RawBuffer_f32_1_1t(target("dx.RawBuffer", float, 1, 1), i8) diff --git a/clang/test/CodeGenHLSL/resource-bindings.hlsl b/clang/test/CodeGenHLSL/resource-bindings.hlsl index d4e63082106538..4049a87a8ab712 100644 --- a/clang/test/CodeGenHLSL/resource-bindings.hlsl +++ b/clang/test/CodeGenHLSL/resource-bindings.hlsl @@ -2,18 +2,18 @@ // CHECK: define internal void @_init_resource_bindings() { -// CHECK: %U0S0_h = call target("dx.TypedBuffer", <4 x float>, 1, 0, 0) @llvm.dx.handle.fromBinding.tdx.TypedBuffer_v4f32_1_0_0t(i32 0, i32 0, i32 1, i32 0, i1 false) +// CHECK: %U0S0_h = call target("dx.TypedBuffer", <4 x float>, 1, 0, 0) @llvm.dx.resource.handlefrombinding.tdx.TypedBuffer_v4f32_1_0_0t(i32 0, i32 0, i32 1, i32 0, i1 false) RWBuffer U0S0 : register(u0); -// CHECK: %U5S3_h = call target("dx.TypedBuffer", float, 1, 0, 0) @llvm.dx.handle.fromBinding.tdx.TypedBuffer_f32_1_0_0t(i32 3, i32 5, i32 1, i32 0, i1 false) +// CHECK: %U5S3_h = call target("dx.TypedBuffer", float, 1, 0, 0) @llvm.dx.resource.handlefrombinding.tdx.TypedBuffer_f32_1_0_0t(i32 3, i32 5, i32 1, i32 0, i1 false) RWBuffer U5S3 : register(u5, space3); -// CHECK: %T2S2_h = call target("dx.RawBuffer", i32, 0, 0) @llvm.dx.handle.fromBinding.tdx.RawBuffer_i32_0_0t(i32 2, i32 2, i32 1, i32 0, i1 false) +// CHECK: %T2S2_h = call target("dx.RawBuffer", i32, 0, 0) @llvm.dx.resource.handlefrombinding.tdx.RawBuffer_i32_0_0t(i32 2, i32 2, i32 1, i32 0, i1 false) StructuredBuffer T2S2 : register(t2, space2); struct S { float4 f; int i; }; -// CHECK: %T3S0_h = call target("dx.RawBuffer", %struct.S, 0, 0) @llvm.dx.handle.fromBinding.tdx.RawBuffer_s_struct.Ss_0_0t(i32 0, i32 3, i32 1, i32 0, i1 false) +// CHECK: %T3S0_h = call target("dx.RawBuffer", %struct.S, 0, 0) @llvm.dx.resource.handlefrombinding.tdx.RawBuffer_s_struct.Ss_0_0t(i32 0, i32 3, i32 1, i32 0, i1 false) StructuredBuffer T3S0 : register(t3); diff --git a/llvm/docs/DirectX/DXILResources.rst b/llvm/docs/DirectX/DXILResources.rst index dcec9611d8aaa0..3971d3788b8a0d 100644 --- a/llvm/docs/DirectX/DXILResources.rst +++ b/llvm/docs/DirectX/DXILResources.rst @@ -154,7 +154,7 @@ We provide a few different ways to instantiate resources in the IR via the type, returning an appropriate handle for the resource, and represent binding information in the arguments to the intrinsic. -The three operations we need are ``llvm.dx.handle.fromBinding``, +The three operations we need are ``llvm.dx.resource.handlefrombinding``, ``llvm.dx.handle.fromHeap``, and ``llvm.dx.handle.fromPointer``. These are rougly equivalent to the DXIL operations ``dx.op.createHandleFromBinding``, ``dx.op.createHandleFromHeap``, and ``dx.op.createHandleForLib``, but they fold @@ -169,7 +169,7 @@ arguments. .. _dx.op.createHandle: https://github.com/microsoft/DirectXShaderCompiler/blob/main/docs/DXIL.rst#resource-handles -.. list-table:: ``@llvm.dx.handle.fromBinding`` +.. list-table:: ``@llvm.dx.resource.handlefrombinding`` :header-rows: 1 * - Argument @@ -210,35 +210,35 @@ Examples: ; RWBuffer Buf : register(u5, space3) %buf = call target("dx.TypedBuffer", <4 x float>, 1, 0, 0) - @llvm.dx.handle.fromBinding.tdx.TypedBuffer_f32_1_0( - i32 3, i32 5, i32 1, i32 0, i1 false) + @llvm.dx.resource.handlefrombinding.tdx.TypedBuffer_f32_1_0( + i32 3, i32 5, i32 1, i32 0, i1 false) ; RWBuffer Buf : register(u7, space2) %buf = call target("dx.TypedBuffer", i32, 1, 0, 1) - @llvm.dx.handle.fromBinding.tdx.TypedBuffer_i32_1_0t( - i32 2, i32 7, i32 1, i32 0, i1 false) + @llvm.dx.resource.handlefrombinding.tdx.TypedBuffer_i32_1_0t( + i32 2, i32 7, i32 1, i32 0, i1 false) ; Buffer Buf[24] : register(t3, space5) %buf = call target("dx.TypedBuffer", <4 x i32>, 0, 0, 0) - @llvm.dx.handle.fromBinding.tdx.TypedBuffer_i32_0_0t( - i32 2, i32 7, i32 24, i32 0, i1 false) + @llvm.dx.resource.handlefrombinding.tdx.TypedBuffer_i32_0_0t( + i32 2, i32 7, i32 24, i32 0, i1 false) ; struct S { float4 a; uint4 b; }; ; StructuredBuffer Buf : register(t2, space4) %buf = call target("dx.RawBuffer", {<4 x float>, <4 x i32>}, 0, 0) - @llvm.dx.handle.fromBinding.tdx.RawBuffer_sl_v4f32v4i32s_0_0t( - i32 4, i32 2, i32 1, i32 0, i1 false) + @llvm.dx.resource.handlefrombinding.tdx.RawBuffer_sl_v4f32v4i32s_0_0t( + i32 4, i32 2, i32 1, i32 0, i1 false) ; ByteAddressBuffer Buf : register(t8, space1) %buf = call target("dx.RawBuffer", i8, 0, 0) - @llvm.dx.handle.fromBinding.tdx.RawBuffer_i8_0_0t( - i32 1, i32 8, i32 1, i32 0, i1 false) + @llvm.dx.resource.handlefrombinding.tdx.RawBuffer_i8_0_0t( + i32 1, i32 8, i32 1, i32 0, i1 false) ; RWBuffer Global[3] : register(u6, space5) ; RWBuffer Buf = Global[2]; %buf = call target("dx.TypedBuffer", <4 x float>, 1, 0, 0) - @llvm.dx.handle.fromBinding.tdx.TypedBuffer_f32_1_0( - i32 5, i32 6, i32 3, i32 2, i1 false) + @llvm.dx.resource.handlefrombinding.tdx.TypedBuffer_f32_1_0( + i32 5, i32 6, i32 3, i32 2, i1 false) .. list-table:: ``@llvm.dx.handle.fromHeap`` :header-rows: 1 @@ -291,10 +291,10 @@ containing 4 elements of the same type, and in the case of `ResRet` a 5th element that is used by the `CheckAccessFullyMapped`_ operation. In LLVM IR the intrinsics will return the contained type of the resource -instead. That is, ``llvm.dx.typedBufferLoad`` from a ``Buffer`` would -return a single float, from ``Buffer`` a vector of 4 floats, and from -``Buffer`` a vector of two doubles, etc. The operations are then -expanded out to match DXIL's format during lowering. +instead. That is, ``llvm.dx.resource.load.typedbuffer`` from a +``Buffer`` would return a single float, from ``Buffer`` a vector +of 4 floats, and from ``Buffer`` a vector of two doubles, etc. The +operations are then expanded out to match DXIL's format during lowering. In cases where we need ``CheckAccessFullyMapped``, we have a second intrinsic that returns an anonymous struct with element-0 being the contained type, and @@ -308,7 +308,7 @@ HLSL source, but this actually matches DXC's behaviour in practice. .. _CBufRet: https://github.com/microsoft/DirectXShaderCompiler/blob/main/docs/DXIL.rst#cbufferloadlegacy .. _CheckAccessFullyMapped: https://learn.microsoft.com/en-us/windows/win32/direct3dhlsl/checkaccessfullymapped -.. list-table:: ``@llvm.dx.typedBufferLoad`` +.. list-table:: ``@llvm.dx.resource.load.typedbuffer`` :header-rows: 1 * - Argument @@ -333,22 +333,22 @@ Examples: .. code-block:: llvm %ret = call <4 x float> - @llvm.dx.typedBufferLoad.v4f32.tdx.TypedBuffer_v4f32_0_0_0t( + @llvm.dx.resource.load.typedbuffer.v4f32.tdx.TypedBuffer_v4f32_0_0_0t( target("dx.TypedBuffer", <4 x float>, 0, 0, 0) %buffer, i32 %index) %ret = call float - @llvm.dx.typedBufferLoad.f32.tdx.TypedBuffer_f32_0_0_0t( + @llvm.dx.resource.load.typedbuffer.f32.tdx.TypedBuffer_f32_0_0_0t( target("dx.TypedBuffer", float, 0, 0, 0) %buffer, i32 %index) %ret = call <4 x i32> - @llvm.dx.typedBufferLoad.v4i32.tdx.TypedBuffer_v4i32_0_0_0t( + @llvm.dx.resource.load.typedbuffer.v4i32.tdx.TypedBuffer_v4i32_0_0_0t( target("dx.TypedBuffer", <4 x i32>, 0, 0, 0) %buffer, i32 %index) %ret = call <4 x half> - @llvm.dx.typedBufferLoad.v4f16.tdx.TypedBuffer_v4f16_0_0_0t( + @llvm.dx.resource.load.typedbuffer.v4f16.tdx.TypedBuffer_v4f16_0_0_0t( target("dx.TypedBuffer", <4 x half>, 0, 0, 0) %buffer, i32 %index) %ret = call <2 x double> - @llvm.dx.typedBufferLoad.v2f64.tdx.TypedBuffer_v2f64_0_0t( + @llvm.dx.resource.load.typedbuffer.v2f64.tdx.TypedBuffer_v2f64_0_0t( target("dx.TypedBuffer", <2 x double>, 0, 0, 0) %buffer, i32 %index) -.. list-table:: ``@llvm.dx.typedBufferLoad.checkbit`` +.. list-table:: ``@llvm.dx.resource.loadchecked.typedbuffer`` :header-rows: 1 * - Argument @@ -371,7 +371,7 @@ Examples: .. code-block:: llvm %ret = call {<4 x float>, i1} - @llvm.dx.typedBufferLoad.checkbit.v4f32.tdx.TypedBuffer_v4f32_0_0_0t( + @llvm.dx.resource.loadchecked.typedbuffer.v4f32.tdx.TypedBuffer_v4f32_0_0_0t( target("dx.TypedBuffer", <4 x float>, 0, 0, 0) %buffer, i32 %index) Texture and Typed Buffer Stores @@ -397,7 +397,7 @@ types that are 32-bits or fewer, such as ``<4 x i32>``, ``<4 x float>``, and Examples: -.. list-table:: ``@llvm.dx.typedBufferStore`` +.. list-table:: ``@llvm.dx.resource.store.typedbuffer`` :header-rows: 1 * - Argument @@ -425,9 +425,9 @@ Examples: .. code-block:: llvm - call void @llvm.dx.typedBufferStore.tdx.Buffer_v4f32_1_0_0t( + call void @llvm.dx.resource.store.typedbuffer.tdx.Buffer_v4f32_1_0_0t( target("dx.TypedBuffer", f32, 1, 0) %buf, i32 %index, <4 x f32> %data) - call void @llvm.dx.typedBufferStore.tdx.Buffer_v4f16_1_0_0t( + call void @llvm.dx.resource.store.typedbuffer.tdx.Buffer_v4f16_1_0_0t( target("dx.TypedBuffer", f16, 1, 0) %buf, i32 %index, <4 x f16> %data) - call void @llvm.dx.typedBufferStore.tdx.Buffer_v2f64_1_0_0t( + call void @llvm.dx.resource.store.typedbuffer.tdx.Buffer_v2f64_1_0_0t( target("dx.TypedBuffer", f64, 1, 0) %buf, i32 %index, <2 x f64> %data) diff --git a/llvm/docs/SPIRVUsage.rst b/llvm/docs/SPIRVUsage.rst index b7b3d21545168c..23c5fe37a9b878 100644 --- a/llvm/docs/SPIRVUsage.rst +++ b/llvm/docs/SPIRVUsage.rst @@ -395,7 +395,7 @@ SPIR-V backend, along with their descriptions and argument details. - Pointer - `[8-bit Integer]` - Creates a resource handle for graphics or compute resources. Facilitates the management and use of resources in shaders. - * - `int_spv_handle_fromBinding` + * - `int_spv_resource_handlefrombinding` - spirv.Image - `[32-bit Integer set, 32-bit Integer binding, 32-bit Integer arraySize, 32-bit Integer index, bool isUniformIndex]` - Returns the handle for the resource at the given set and binding.\ @@ -410,7 +410,7 @@ SPIR-V backend, along with their descriptions and argument details. return type is a scalar, then the first element of the vector is \ returned. If the return type is an n-element vector, then the first \ n-elements of the 4-element vector are returned. - * - `int_spv_typedBufferStore` + * - `int_spv_resource_store_typedbuffer` - void - `[spirv.Image Image, 32-bit Integer coordinate, vec4 data]` - Stores the data to the image buffer at the given coordinate. The \ diff --git a/llvm/include/llvm/IR/IntrinsicsDirectX.td b/llvm/include/llvm/IR/IntrinsicsDirectX.td index d509c17ee36c81..d31d5afe5145a7 100644 --- a/llvm/include/llvm/IR/IntrinsicsDirectX.td +++ b/llvm/include/llvm/IR/IntrinsicsDirectX.td @@ -21,7 +21,7 @@ def int_dx_flattened_thread_id_in_group : Intrinsic<[llvm_i32_ty], [], [IntrNoMe // type appropriate for the kind of resource given a register space ID, lower // bound and range size of the binding, as well as an index and an indicator // whether that index may be non-uniform. -def int_dx_handle_fromBinding +def int_dx_resource_handlefrombinding : DefaultAttrsIntrinsic< [llvm_any_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i1_ty], @@ -30,22 +30,22 @@ def int_dx_handle_fromBinding def int_dx_resource_getpointer : DefaultAttrsIntrinsic<[llvm_anyptr_ty], [llvm_any_ty, llvm_i32_ty], [IntrNoMem]>; -def int_dx_typedBufferLoad +def int_dx_resource_load_typedbuffer : DefaultAttrsIntrinsic<[llvm_any_ty], [llvm_any_ty, llvm_i32_ty], [IntrReadMem]>; -def int_dx_typedBufferLoad_checkbit +def int_dx_resource_loadchecked_typedbuffer : DefaultAttrsIntrinsic<[llvm_any_ty, llvm_i1_ty], [llvm_any_ty, llvm_i32_ty], [IntrReadMem]>; -def int_dx_typedBufferStore +def int_dx_resource_store_typedbuffer : DefaultAttrsIntrinsic<[], [llvm_any_ty, llvm_i32_ty, llvm_anyvector_ty], [IntrWriteMem]>; -def int_dx_bufferUpdateCounter +def int_dx_resource_updatecounter : DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_any_ty, llvm_i8_ty], [IntrInaccessibleMemOrArgMemOnly]>; // Cast between target extension handle types and dxil-style opaque handles -def int_dx_cast_handle : Intrinsic<[llvm_any_ty], [llvm_any_ty]>; +def int_dx_resource_casthandle : Intrinsic<[llvm_any_ty], [llvm_any_ty]>; def int_dx_all : DefaultAttrsIntrinsic<[llvm_i1_ty], [llvm_any_ty], [IntrNoMem]>; def int_dx_any : DefaultAttrsIntrinsic<[llvm_i1_ty], [llvm_any_ty], [IntrNoMem]>; diff --git a/llvm/include/llvm/IR/IntrinsicsSPIRV.td b/llvm/include/llvm/IR/IntrinsicsSPIRV.td index 3895ad6ee297a1..bcff0f20b985d4 100644 --- a/llvm/include/llvm/IR/IntrinsicsSPIRV.td +++ b/llvm/include/llvm/IR/IntrinsicsSPIRV.td @@ -103,7 +103,7 @@ let TargetPrefix = "spv" in { // type appropriate for the kind of resource given the set id, binding id, // array size of the binding, as well as an index and an indicator // whether that index may be non-uniform. - def int_spv_handle_fromBinding + def int_spv_resource_handlefrombinding : DefaultAttrsIntrinsic< [llvm_any_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i1_ty], @@ -112,19 +112,19 @@ let TargetPrefix = "spv" in { def int_spv_firstbituhigh : DefaultAttrsIntrinsic<[LLVMScalarOrSameVectorWidth<0, llvm_i32_ty>], [llvm_anyint_ty], [IntrNoMem]>; def int_spv_firstbitshigh : DefaultAttrsIntrinsic<[LLVMScalarOrSameVectorWidth<0, llvm_i32_ty>], [llvm_anyint_ty], [IntrNoMem]>; - def int_spv_bufferUpdateCounter + def int_spv_resource_updatecounter : DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_any_ty, llvm_i8_ty], [IntrInaccessibleMemOrArgMemOnly]>; // Read a value from the image buffer. It does not translate directly to a // single OpImageRead because the result type is not necessarily a 4 element // vector. - def int_spv_typedBufferLoad + def int_spv_resource_load_typedbuffer : DefaultAttrsIntrinsic<[llvm_any_ty], [llvm_any_ty, llvm_i32_ty]>; // Write a value to the image buffer. Translates directly to a single // OpImageWrite. - def int_spv_typedBufferStore + def int_spv_resource_store_typedbuffer : DefaultAttrsIntrinsic<[], [llvm_any_ty, llvm_i32_ty, llvm_anyvector_ty]>; } diff --git a/llvm/lib/Analysis/DXILResource.cpp b/llvm/lib/Analysis/DXILResource.cpp index b6d98407fe809e..7f28e63cc117d4 100644 --- a/llvm/lib/Analysis/DXILResource.cpp +++ b/llvm/lib/Analysis/DXILResource.cpp @@ -691,7 +691,7 @@ void DXILBindingMap::populate(Module &M, DXILResourceTypeMap &DRTM) { switch (ID) { default: continue; - case Intrinsic::dx_handle_fromBinding: { + case Intrinsic::dx_resource_handlefrombinding: { auto *HandleTy = cast(F.getReturnType()); ResourceTypeInfo &RTI = DRTM[HandleTy]; diff --git a/llvm/lib/Target/DirectX/DXILOpLowering.cpp b/llvm/lib/Target/DirectX/DXILOpLowering.cpp index c283b9081e0871..4e01dd1145a55c 100644 --- a/llvm/lib/Target/DirectX/DXILOpLowering.cpp +++ b/llvm/lib/Target/DirectX/DXILOpLowering.cpp @@ -191,7 +191,7 @@ class OpLowerer { /// or defs, and by the end all of the casts will be redundant. Value *createTmpHandleCast(Value *V, Type *Ty) { CallInst *Cast = OpBuilder.getIRB().CreateIntrinsic( - Intrinsic::dx_cast_handle, {Ty, V->getType()}, {V}); + Intrinsic::dx_resource_casthandle, {Ty, V->getType()}, {V}); CleanupCasts.push_back(Cast); return Cast; } @@ -216,7 +216,7 @@ class OpLowerer { // Otherwise, we're the second handle in a pair. Forward the arguments and // remove the (second) cast. CallInst *Def = cast(Cast->getOperand(0)); - assert(Def->getIntrinsicID() == Intrinsic::dx_cast_handle && + assert(Def->getIntrinsicID() == Intrinsic::dx_resource_casthandle && "Unbalanced pair of temporary handle casts"); Cast->replaceAllUsesWith(Def->getOperand(0)); Cast->eraseFromParent(); @@ -349,8 +349,9 @@ class OpLowerer { }); } - /// Lower `dx.handle.fromBinding` intrinsics depending on the shader model and - /// taking into account binding information from DXILResourceBindingAnalysis. + /// Lower `dx.resource.handlefrombinding` intrinsics depending on the shader + /// model and taking into account binding information from + /// DXILResourceBindingAnalysis. bool lowerHandleFromBinding(Function &F) { Triple TT(Triple(M.getTargetTriple())); if (TT.getDXILVersion() < VersionTuple(1, 6)) @@ -715,22 +716,22 @@ class OpLowerer { F, OpCode, ArrayRef{__VA_ARGS__}); \ break; #include "DXILOperation.inc" - case Intrinsic::dx_handle_fromBinding: + case Intrinsic::dx_resource_handlefrombinding: HasErrors |= lowerHandleFromBinding(F); break; case Intrinsic::dx_resource_getpointer: HasErrors |= lowerGetPointer(F); break; - case Intrinsic::dx_typedBufferLoad: + case Intrinsic::dx_resource_load_typedbuffer: HasErrors |= lowerTypedBufferLoad(F, /*HasCheckBit=*/false); break; - case Intrinsic::dx_typedBufferLoad_checkbit: + case Intrinsic::dx_resource_loadchecked_typedbuffer: HasErrors |= lowerTypedBufferLoad(F, /*HasCheckBit=*/true); break; - case Intrinsic::dx_typedBufferStore: + case Intrinsic::dx_resource_store_typedbuffer: HasErrors |= lowerTypedBufferStore(F); break; - case Intrinsic::dx_bufferUpdateCounter: + case Intrinsic::dx_resource_updatecounter: HasErrors |= lowerUpdateCounter(F); break; // TODO: this can be removed when diff --git a/llvm/lib/Target/DirectX/DXILResourceAccess.cpp b/llvm/lib/Target/DirectX/DXILResourceAccess.cpp index 7e9f9e1593e967..1ff8f09f066db5 100644 --- a/llvm/lib/Target/DirectX/DXILResourceAccess.cpp +++ b/llvm/lib/Target/DirectX/DXILResourceAccess.cpp @@ -81,7 +81,7 @@ static void replaceTypedBufferAccess(IntrinsicInst *II, // We're storing a scalar, so we need to load the current value and only // replace the relevant part. auto *Load = Builder.CreateIntrinsic( - ContainedType, Intrinsic::dx_typedBufferLoad, + ContainedType, Intrinsic::dx_resource_load_typedbuffer, {II->getOperand(0), II->getOperand(1)}); // If we have an offset from seeing a GEP earlier, use it. Value *IndexOp = Current.Index @@ -93,16 +93,16 @@ static void replaceTypedBufferAccess(IntrinsicInst *II, } auto *Inst = Builder.CreateIntrinsic( - Builder.getVoidTy(), Intrinsic::dx_typedBufferStore, + Builder.getVoidTy(), Intrinsic::dx_resource_store_typedbuffer, {II->getOperand(0), II->getOperand(1), V}); SI->replaceAllUsesWith(Inst); DeadInsts.push_back(SI); } else if (auto *LI = dyn_cast(Current.Access)) { IRBuilder<> Builder(LI); - Value *V = - Builder.CreateIntrinsic(ContainedType, Intrinsic::dx_typedBufferLoad, - {II->getOperand(0), II->getOperand(1)}); + Value *V = Builder.CreateIntrinsic( + ContainedType, Intrinsic::dx_resource_load_typedbuffer, + {II->getOperand(0), II->getOperand(1)}); if (Current.Index) V = Builder.CreateExtractElement(V, Current.Index); diff --git a/llvm/lib/Target/DirectX/DXILShaderFlags.cpp b/llvm/lib/Target/DirectX/DXILShaderFlags.cpp index 1e88963345763f..2edfc707ce6c79 100644 --- a/llvm/lib/Target/DirectX/DXILShaderFlags.cpp +++ b/llvm/lib/Target/DirectX/DXILShaderFlags.cpp @@ -54,7 +54,7 @@ static void updateFunctionFlags(ComputedShaderFlags &CSF, const Instruction &I, switch (II->getIntrinsicID()) { default: break; - case Intrinsic::dx_typedBufferLoad: { + case Intrinsic::dx_resource_load_typedbuffer: { dxil::ResourceTypeInfo &RTI = DRTM[cast(II->getArgOperand(0)->getType())]; if (RTI.isTyped()) diff --git a/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp b/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp index b593b9bd1d7aab..289d5f31664872 100644 --- a/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp +++ b/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp @@ -2987,14 +2987,14 @@ bool SPIRVInstructionSelector::selectIntrinsic(Register ResVReg, // Discard internal intrinsics. case Intrinsic::spv_value_md: break; - case Intrinsic::spv_handle_fromBinding: { + case Intrinsic::spv_resource_handlefrombinding: { return selectHandleFromBinding(ResVReg, ResType, I); } - case Intrinsic::spv_typedBufferStore: { + case Intrinsic::spv_resource_store_typedbuffer: { selectImageWriteIntrinsic(I); return true; } - case Intrinsic::spv_typedBufferLoad: { + case Intrinsic::spv_resource_load_typedbuffer: { selectReadImageIntrinsic(ResVReg, ResType, I); return true; } diff --git a/llvm/test/Analysis/DXILResource/buffer-frombinding.ll b/llvm/test/Analysis/DXILResource/buffer-frombinding.ll index 313c8376483b91..ab7151c57473fc 100644 --- a/llvm/test/Analysis/DXILResource/buffer-frombinding.ll +++ b/llvm/test/Analysis/DXILResource/buffer-frombinding.ll @@ -5,7 +5,7 @@ define void @test_typedbuffer() { ; ByteAddressBuffer Buf : register(t8, space1) %srv0 = call target("dx.RawBuffer", void, 0, 0) - @llvm.dx.handle.fromBinding.tdx.RawBuffer_i8_0_0t( + @llvm.dx.resource.handlefrombinding.tdx.RawBuffer_i8_0_0t( i32 1, i32 8, i32 1, i32 0, i1 false) ; CHECK: Binding [[SRV0:[0-9]+]]: ; CHECK: Binding: @@ -19,7 +19,7 @@ define void @test_typedbuffer() { ; struct S { float4 a; uint4 b; }; ; StructuredBuffer Buf : register(t2, space4) %srv1 = call target("dx.RawBuffer", {<4 x float>, <4 x i32>}, 0, 0) - @llvm.dx.handle.fromBinding.tdx.RawBuffer_sl_v4f32v4i32s_0_0t( + @llvm.dx.resource.handlefrombinding.tdx.RawBuffer_sl_v4f32v4i32s_0_0t( i32 4, i32 2, i32 1, i32 0, i1 false) ; CHECK: Binding [[SRV1:[0-9]+]]: ; CHECK: Binding: @@ -34,7 +34,7 @@ define void @test_typedbuffer() { ; Buffer Buf[24] : register(t3, space5) %srv2 = call target("dx.TypedBuffer", <4 x i32>, 0, 0, 0) - @llvm.dx.handle.fromBinding.tdx.TypedBuffer_i32_0_0t( + @llvm.dx.resource.handlefrombinding.tdx.TypedBuffer_i32_0_0t( i32 5, i32 3, i32 24, i32 0, i1 false) ; CHECK: Binding [[SRV2:[0-9]+]]: ; CHECK: Binding: @@ -49,7 +49,7 @@ define void @test_typedbuffer() { ; RWBuffer Buf : register(u7, space2) %uav0 = call target("dx.TypedBuffer", i32, 1, 0, 1) - @llvm.dx.handle.fromBinding.tdx.TypedBuffer_i32_1_0t( + @llvm.dx.resource.handlefrombinding.tdx.TypedBuffer_i32_1_0t( i32 2, i32 7, i32 1, i32 0, i1 false) ; CHECK: Binding [[UAV0:[0-9]+]]: ; CHECK: Binding: @@ -67,7 +67,7 @@ define void @test_typedbuffer() { ; RWBuffer Buf : register(u5, space3) %uav1 = call target("dx.TypedBuffer", <4 x float>, 1, 0, 0) - @llvm.dx.handle.fromBinding.tdx.TypedBuffer_f32_1_0( + @llvm.dx.resource.handlefrombinding.tdx.TypedBuffer_f32_1_0( i32 3, i32 5, i32 1, i32 0, i1 false) ; CHECK: Binding [[UAV1:[0-9]+]]: ; CHECK: Binding: @@ -86,11 +86,11 @@ define void @test_typedbuffer() { ; RWBuffer BufferArray[10] : register(u0, space4) ; RWBuffer Buf = BufferArray[0] %uav2_1 = call target("dx.TypedBuffer", <4 x float>, 1, 0, 0) - @llvm.dx.handle.fromBinding.tdx.TypedBuffer_f32_1_0( + @llvm.dx.resource.handlefrombinding.tdx.TypedBuffer_f32_1_0( i32 4, i32 0, i32 10, i32 0, i1 false) ; RWBuffer Buf = BufferArray[5] %uav2_2 = call target("dx.TypedBuffer", <4 x float>, 1, 0, 0) - @llvm.dx.handle.fromBinding.tdx.TypedBuffer_f32_1_0( + @llvm.dx.resource.handlefrombinding.tdx.TypedBuffer_f32_1_0( i32 4, i32 0, i32 10, i32 5, i1 false) ; CHECK: Binding [[UAV2:[0-9]+]]: ; CHECK: Binding: diff --git a/llvm/test/CodeGen/DirectX/BufferLoad.ll b/llvm/test/CodeGen/DirectX/BufferLoad.ll index 24d65fe1648c15..7f1291bf4a5c8f 100644 --- a/llvm/test/CodeGen/DirectX/BufferLoad.ll +++ b/llvm/test/CodeGen/DirectX/BufferLoad.ll @@ -10,14 +10,14 @@ define void @loadv4f32() { ; CHECK: [[BIND:%.*]] = call %dx.types.Handle @dx.op.createHandleFromBinding(i32 217, ; CHECK: [[HANDLE:%.*]] = call %dx.types.Handle @dx.op.annotateHandle(i32 216, %dx.types.Handle [[BIND]] %buffer = call target("dx.TypedBuffer", <4 x float>, 0, 0, 0) - @llvm.dx.handle.fromBinding.tdx.TypedBuffer_v4f32_0_0_0( + @llvm.dx.resource.handlefrombinding.tdx.TypedBuffer_v4f32_0_0_0( i32 0, i32 0, i32 1, i32 0, i1 false) ; The temporary casts should all have been cleaned up - ; CHECK-NOT: %dx.cast_handle + ; CHECK-NOT: %dx.resource.casthandle ; CHECK: [[DATA0:%.*]] = call %dx.types.ResRet.f32 @dx.op.bufferLoad.f32(i32 68, %dx.types.Handle [[HANDLE]], i32 0, i32 undef) - %data0 = call <4 x float> @llvm.dx.typedBufferLoad( + %data0 = call <4 x float> @llvm.dx.resource.load.typedbuffer( target("dx.TypedBuffer", <4 x float>, 0, 0, 0) %buffer, i32 0) ; The extract order depends on the users, so don't enforce that here. @@ -34,7 +34,7 @@ define void @loadv4f32() { call void @scalar_user(float %data0_2) ; CHECK: [[DATA4:%.*]] = call %dx.types.ResRet.f32 @dx.op.bufferLoad.f32(i32 68, %dx.types.Handle [[HANDLE]], i32 4, i32 undef) - %data4 = call <4 x float> @llvm.dx.typedBufferLoad( + %data4 = call <4 x float> @llvm.dx.resource.load.typedbuffer( target("dx.TypedBuffer", <4 x float>, 0, 0, 0) %buffer, i32 4) ; CHECK: extractvalue %dx.types.ResRet.f32 [[DATA4]], 0 @@ -48,7 +48,7 @@ define void @loadv4f32() { call void @vector_user(<4 x float> %data4) ; CHECK: [[DATA12:%.*]] = call %dx.types.ResRet.f32 @dx.op.bufferLoad.f32(i32 68, %dx.types.Handle [[HANDLE]], i32 12, i32 undef) - %data12 = call <4 x float> @llvm.dx.typedBufferLoad( + %data12 = call <4 x float> @llvm.dx.resource.load.typedbuffer( target("dx.TypedBuffer", <4 x float>, 0, 0, 0) %buffer, i32 12) ; CHECK: [[DATA12_3:%.*]] = extractvalue %dx.types.ResRet.f32 [[DATA12]], 3 @@ -66,11 +66,11 @@ define void @index_dynamic(i32 %bufindex, i32 %elemindex) { ; CHECK: [[BIND:%.*]] = call %dx.types.Handle @dx.op.createHandleFromBinding(i32 217, ; CHECK: [[HANDLE:%.*]] = call %dx.types.Handle @dx.op.annotateHandle(i32 216, %dx.types.Handle [[BIND]] %buffer = call target("dx.TypedBuffer", <4 x float>, 0, 0, 0) - @llvm.dx.handle.fromBinding.tdx.TypedBuffer_v4f32_0_0_0( + @llvm.dx.resource.handlefrombinding.tdx.TypedBuffer_v4f32_0_0_0( i32 0, i32 0, i32 1, i32 0, i1 false) ; CHECK: [[LOAD:%.*]] = call %dx.types.ResRet.f32 @dx.op.bufferLoad.f32(i32 68, %dx.types.Handle [[HANDLE]], i32 %bufindex, i32 undef) - %load = call <4 x float> @llvm.dx.typedBufferLoad( + %load = call <4 x float> @llvm.dx.resource.load.typedbuffer( target("dx.TypedBuffer", <4 x float>, 0, 0, 0) %buffer, i32 %bufindex) ; CHECK: [[ALLOCA:%.*]] = alloca [4 x float] @@ -101,11 +101,11 @@ define void @loadf32() { ; CHECK: [[BIND:%.*]] = call %dx.types.Handle @dx.op.createHandleFromBinding(i32 217, ; CHECK: [[HANDLE:%.*]] = call %dx.types.Handle @dx.op.annotateHandle(i32 216, %dx.types.Handle [[BIND]] %buffer = call target("dx.TypedBuffer", float, 0, 0, 0) - @llvm.dx.handle.fromBinding.tdx.TypedBuffer_f32_0_0_0( + @llvm.dx.resource.handlefrombinding.tdx.TypedBuffer_f32_0_0_0( i32 0, i32 0, i32 1, i32 0, i1 false) ; CHECK: [[DATA0:%.*]] = call %dx.types.ResRet.f32 @dx.op.bufferLoad.f32(i32 68, %dx.types.Handle [[HANDLE]], i32 0, i32 undef) - %data0 = call float @llvm.dx.typedBufferLoad( + %data0 = call float @llvm.dx.resource.load.typedbuffer( target("dx.TypedBuffer", float, 0, 0, 0) %buffer, i32 0) ; CHECK: [[VAL0:%.*]] = extractvalue %dx.types.ResRet.f32 [[DATA0]], 0 @@ -119,11 +119,11 @@ define void @loadv2f32() { ; CHECK: [[BIND:%.*]] = call %dx.types.Handle @dx.op.createHandleFromBinding(i32 217, ; CHECK: [[HANDLE:%.*]] = call %dx.types.Handle @dx.op.annotateHandle(i32 216, %dx.types.Handle [[BIND]] %buffer = call target("dx.TypedBuffer", <2 x float>, 0, 0, 0) - @llvm.dx.handle.fromBinding.tdx.TypedBuffer_v2f32_0_0_0( + @llvm.dx.resource.handlefrombinding.tdx.TypedBuffer_v2f32_0_0_0( i32 0, i32 0, i32 1, i32 0, i1 false) ; CHECK: [[DATA0:%.*]] = call %dx.types.ResRet.f32 @dx.op.bufferLoad.f32(i32 68, %dx.types.Handle [[HANDLE]], i32 0, i32 undef) - %data0 = call <2 x float> @llvm.dx.typedBufferLoad( + %data0 = call <2 x float> @llvm.dx.resource.load.typedbuffer( target("dx.TypedBuffer", <2 x float>, 0, 0, 0) %buffer, i32 0) ret void @@ -133,11 +133,11 @@ define void @loadv4f32_checkbit() { ; CHECK: [[BIND:%.*]] = call %dx.types.Handle @dx.op.createHandleFromBinding(i32 217, ; CHECK: [[HANDLE:%.*]] = call %dx.types.Handle @dx.op.annotateHandle(i32 216, %dx.types.Handle [[BIND]] %buffer = call target("dx.TypedBuffer", <4 x float>, 0, 0, 0) - @llvm.dx.handle.fromBinding.tdx.TypedBuffer_v4f32_0_0_0( + @llvm.dx.resource.handlefrombinding.tdx.TypedBuffer_v4f32_0_0_0( i32 0, i32 0, i32 1, i32 0, i1 false) ; CHECK: [[DATA0:%.*]] = call %dx.types.ResRet.f32 @dx.op.bufferLoad.f32(i32 68, %dx.types.Handle [[HANDLE]], i32 0, i32 undef) - %data0 = call {<4 x float>, i1} @llvm.dx.typedBufferLoad.checkbit.f32( + %data0 = call {<4 x float>, i1} @llvm.dx.resource.loadchecked.typedbuffer.f32( target("dx.TypedBuffer", <4 x float>, 0, 0, 0) %buffer, i32 0) ; CHECK: [[STATUS:%.*]] = extractvalue %dx.types.ResRet.f32 [[DATA0]], 4 @@ -154,11 +154,11 @@ define void @loadv4i32() { ; CHECK: [[BIND:%.*]] = call %dx.types.Handle @dx.op.createHandleFromBinding(i32 217, ; CHECK: [[HANDLE:%.*]] = call %dx.types.Handle @dx.op.annotateHandle(i32 216, %dx.types.Handle [[BIND]] %buffer = call target("dx.TypedBuffer", <4 x i32>, 0, 0, 0) - @llvm.dx.handle.fromBinding.tdx.TypedBuffer_v4i32_0_0_0( + @llvm.dx.resource.handlefrombinding.tdx.TypedBuffer_v4i32_0_0_0( i32 0, i32 0, i32 1, i32 0, i1 false) ; CHECK: [[DATA0:%.*]] = call %dx.types.ResRet.i32 @dx.op.bufferLoad.i32(i32 68, %dx.types.Handle [[HANDLE]], i32 0, i32 undef) - %data0 = call <4 x i32> @llvm.dx.typedBufferLoad( + %data0 = call <4 x i32> @llvm.dx.resource.load.typedbuffer( target("dx.TypedBuffer", <4 x i32>, 0, 0, 0) %buffer, i32 0) ret void @@ -168,11 +168,11 @@ define void @loadv4f16() { ; CHECK: [[BIND:%.*]] = call %dx.types.Handle @dx.op.createHandleFromBinding(i32 217, ; CHECK: [[HANDLE:%.*]] = call %dx.types.Handle @dx.op.annotateHandle(i32 216, %dx.types.Handle [[BIND]] %buffer = call target("dx.TypedBuffer", <4 x half>, 0, 0, 0) - @llvm.dx.handle.fromBinding.tdx.TypedBuffer_v4f16_0_0_0( + @llvm.dx.resource.handlefrombinding.tdx.TypedBuffer_v4f16_0_0_0( i32 0, i32 0, i32 1, i32 0, i1 false) ; CHECK: [[DATA0:%.*]] = call %dx.types.ResRet.f16 @dx.op.bufferLoad.f16(i32 68, %dx.types.Handle [[HANDLE]], i32 0, i32 undef) - %data0 = call <4 x half> @llvm.dx.typedBufferLoad( + %data0 = call <4 x half> @llvm.dx.resource.load.typedbuffer( target("dx.TypedBuffer", <4 x half>, 0, 0, 0) %buffer, i32 0) ret void @@ -182,11 +182,11 @@ define void @loadv4i16() { ; CHECK: [[BIND:%.*]] = call %dx.types.Handle @dx.op.createHandleFromBinding(i32 217, ; CHECK: [[HANDLE:%.*]] = call %dx.types.Handle @dx.op.annotateHandle(i32 216, %dx.types.Handle [[BIND]] %buffer = call target("dx.TypedBuffer", <4 x i16>, 0, 0, 0) - @llvm.dx.handle.fromBinding.tdx.TypedBuffer_v4i16_0_0_0( + @llvm.dx.resource.handlefrombinding.tdx.TypedBuffer_v4i16_0_0_0( i32 0, i32 0, i32 1, i32 0, i1 false) ; CHECK: [[DATA0:%.*]] = call %dx.types.ResRet.i16 @dx.op.bufferLoad.i16(i32 68, %dx.types.Handle [[HANDLE]], i32 0, i32 undef) - %data0 = call <4 x i16> @llvm.dx.typedBufferLoad( + %data0 = call <4 x i16> @llvm.dx.resource.load.typedbuffer( target("dx.TypedBuffer", <4 x i16>, 0, 0, 0) %buffer, i32 0) ret void diff --git a/llvm/test/CodeGen/DirectX/BufferStore-errors.ll b/llvm/test/CodeGen/DirectX/BufferStore-errors.ll index ffdcb037b8968e..6e529973bd604e 100644 --- a/llvm/test/CodeGen/DirectX/BufferStore-errors.ll +++ b/llvm/test/CodeGen/DirectX/BufferStore-errors.ll @@ -8,10 +8,10 @@ target triple = "dxil-pc-shadermodel6.6-compute" ; CHECK-SAME: typedBufferStore data must be a vector of 4 elements define void @storetoomany(<5 x float> %data, i32 %index) "hlsl.export" { %buffer = call target("dx.TypedBuffer", <4 x float>, 1, 0, 0) - @llvm.dx.handle.fromBinding.tdx.TypedBuffer_v4f32_1_0_0( + @llvm.dx.resource.handlefrombinding.tdx.TypedBuffer_v4f32_1_0_0( i32 0, i32 0, i32 1, i32 0, i1 false) - call void @llvm.dx.typedBufferStore.tdx.TypedBuffer_v4f32_1_0_0t.v5f32( + call void @llvm.dx.resource.store.typedbuffer.tdx.TypedBuffer_v4f32_1_0_0t.v5f32( target("dx.TypedBuffer", <4 x float>, 1, 0, 0) %buffer, i32 %index, <5 x float> %data) @@ -23,15 +23,15 @@ define void @storetoomany(<5 x float> %data, i32 %index) "hlsl.export" { ; CHECK-SAME: typedBufferStore data must be a vector of 4 elements define void @storetoofew(<3 x i32> %data, i32 %index) "hlsl.export" { %buffer = call target("dx.TypedBuffer", <4 x i32>, 1, 0, 0) - @llvm.dx.handle.fromBinding.tdx.TypedBuffer_v4i32_1_0_0( + @llvm.dx.resource.handlefrombinding.tdx.TypedBuffer_v4i32_1_0_0( i32 0, i32 0, i32 1, i32 0, i1 false) - call void @llvm.dx.typedBufferStore.tdx.TypedBuffer_v4i32_1_0_0t.v3i32( + call void @llvm.dx.resource.store.typedbuffer.tdx.TypedBuffer_v4i32_1_0_0t.v3i32( target("dx.TypedBuffer", <4 x i32>, 1, 0, 0) %buffer, i32 %index, <3 x i32> %data) ret void } -declare void @llvm.dx.typedBufferStore.tdx.TypedBuffer_v4f32_1_0_0t.v5f32(target("dx.TypedBuffer", <4 x float>, 1, 0, 0), i32, <5 x float>) -declare void @llvm.dx.typedBufferStore.tdx.TypedBuffer_v4i32_1_0_0t.v3i32(target("dx.TypedBuffer", <4 x i32>, 1, 0, 0), i32, <3 x i32>) +declare void @llvm.dx.resource.store.typedbuffer.tdx.TypedBuffer_v4f32_1_0_0t.v5f32(target("dx.TypedBuffer", <4 x float>, 1, 0, 0), i32, <5 x float>) +declare void @llvm.dx.resource.store.typedbuffer.tdx.TypedBuffer_v4i32_1_0_0t.v3i32(target("dx.TypedBuffer", <4 x i32>, 1, 0, 0), i32, <3 x i32>) diff --git a/llvm/test/CodeGen/DirectX/BufferStore.ll b/llvm/test/CodeGen/DirectX/BufferStore.ll index 81cc5fd328e0a7..381df6a63962e2 100644 --- a/llvm/test/CodeGen/DirectX/BufferStore.ll +++ b/llvm/test/CodeGen/DirectX/BufferStore.ll @@ -7,18 +7,18 @@ define void @storefloat(<4 x float> %data, i32 %index) { ; CHECK: [[BIND:%.*]] = call %dx.types.Handle @dx.op.createHandleFromBinding(i32 217, ; CHECK: [[HANDLE:%.*]] = call %dx.types.Handle @dx.op.annotateHandle(i32 216, %dx.types.Handle [[BIND]] %buffer = call target("dx.TypedBuffer", <4 x float>, 1, 0, 0) - @llvm.dx.handle.fromBinding.tdx.TypedBuffer_v4f32_1_0_0( + @llvm.dx.resource.handlefrombinding.tdx.TypedBuffer_v4f32_1_0_0( i32 0, i32 0, i32 1, i32 0, i1 false) ; The temporary casts should all have been cleaned up - ; CHECK-NOT: %dx.cast_handle + ; CHECK-NOT: %dx.resource.casthandle ; CHECK: [[DATA0_0:%.*]] = extractelement <4 x float> %data, i32 0 ; CHECK: [[DATA0_1:%.*]] = extractelement <4 x float> %data, i32 1 ; CHECK: [[DATA0_2:%.*]] = extractelement <4 x float> %data, i32 2 ; CHECK: [[DATA0_3:%.*]] = extractelement <4 x float> %data, i32 3 ; CHECK: call void @dx.op.bufferStore.f32(i32 69, %dx.types.Handle [[HANDLE]], i32 %index, i32 undef, float [[DATA0_0]], float [[DATA0_1]], float [[DATA0_2]], float [[DATA0_3]], i8 15) - call void @llvm.dx.typedBufferStore( + call void @llvm.dx.resource.store.typedbuffer( target("dx.TypedBuffer", <4 x float>, 1, 0, 0) %buffer, i32 %index, <4 x float> %data) @@ -30,7 +30,7 @@ define void @storeint(<4 x i32> %data, i32 %index) { ; CHECK: [[BIND:%.*]] = call %dx.types.Handle @dx.op.createHandleFromBinding(i32 217, ; CHECK: [[HANDLE:%.*]] = call %dx.types.Handle @dx.op.annotateHandle(i32 216, %dx.types.Handle [[BIND]] %buffer = call target("dx.TypedBuffer", <4 x i32>, 1, 0, 0) - @llvm.dx.handle.fromBinding.tdx.TypedBuffer_v4i32_1_0_0( + @llvm.dx.resource.handlefrombinding.tdx.TypedBuffer_v4i32_1_0_0( i32 0, i32 0, i32 1, i32 0, i1 false) ; CHECK: [[DATA0_0:%.*]] = extractelement <4 x i32> %data, i32 0 @@ -38,7 +38,7 @@ define void @storeint(<4 x i32> %data, i32 %index) { ; CHECK: [[DATA0_2:%.*]] = extractelement <4 x i32> %data, i32 2 ; CHECK: [[DATA0_3:%.*]] = extractelement <4 x i32> %data, i32 3 ; CHECK: call void @dx.op.bufferStore.i32(i32 69, %dx.types.Handle [[HANDLE]], i32 %index, i32 undef, i32 [[DATA0_0]], i32 [[DATA0_1]], i32 [[DATA0_2]], i32 [[DATA0_3]], i8 15) - call void @llvm.dx.typedBufferStore( + call void @llvm.dx.resource.store.typedbuffer( target("dx.TypedBuffer", <4 x i32>, 1, 0, 0) %buffer, i32 %index, <4 x i32> %data) @@ -50,18 +50,18 @@ define void @storehalf(<4 x half> %data, i32 %index) { ; CHECK: [[BIND:%.*]] = call %dx.types.Handle @dx.op.createHandleFromBinding(i32 217, ; CHECK: [[HANDLE:%.*]] = call %dx.types.Handle @dx.op.annotateHandle(i32 216, %dx.types.Handle [[BIND]] %buffer = call target("dx.TypedBuffer", <4 x half>, 1, 0, 0) - @llvm.dx.handle.fromBinding.tdx.TypedBuffer_v4f16_1_0_0( + @llvm.dx.resource.handlefrombinding.tdx.TypedBuffer_v4f16_1_0_0( i32 0, i32 0, i32 1, i32 0, i1 false) ; The temporary casts should all have been cleaned up - ; CHECK-NOT: %dx.cast_handle + ; CHECK-NOT: %dx.resource.casthandle ; CHECK: [[DATA0_0:%.*]] = extractelement <4 x half> %data, i32 0 ; CHECK: [[DATA0_1:%.*]] = extractelement <4 x half> %data, i32 1 ; CHECK: [[DATA0_2:%.*]] = extractelement <4 x half> %data, i32 2 ; CHECK: [[DATA0_3:%.*]] = extractelement <4 x half> %data, i32 3 ; CHECK: call void @dx.op.bufferStore.f16(i32 69, %dx.types.Handle [[HANDLE]], i32 %index, i32 undef, half [[DATA0_0]], half [[DATA0_1]], half [[DATA0_2]], half [[DATA0_3]], i8 15) - call void @llvm.dx.typedBufferStore( + call void @llvm.dx.resource.store.typedbuffer( target("dx.TypedBuffer", <4 x half>, 1, 0, 0) %buffer, i32 %index, <4 x half> %data) @@ -73,18 +73,18 @@ define void @storei16(<4 x i16> %data, i32 %index) { ; CHECK: [[BIND:%.*]] = call %dx.types.Handle @dx.op.createHandleFromBinding(i32 217, ; CHECK: [[HANDLE:%.*]] = call %dx.types.Handle @dx.op.annotateHandle(i32 216, %dx.types.Handle [[BIND]] %buffer = call target("dx.TypedBuffer", <4 x i16>, 1, 0, 0) - @llvm.dx.handle.fromBinding.tdx.TypedBuffer_v4i16_1_0_0( + @llvm.dx.resource.handlefrombinding.tdx.TypedBuffer_v4i16_1_0_0( i32 0, i32 0, i32 1, i32 0, i1 false) ; The temporary casts should all have been cleaned up - ; CHECK-NOT: %dx.cast_handle + ; CHECK-NOT: %dx.resource.casthandle ; CHECK: [[DATA0_0:%.*]] = extractelement <4 x i16> %data, i32 0 ; CHECK: [[DATA0_1:%.*]] = extractelement <4 x i16> %data, i32 1 ; CHECK: [[DATA0_2:%.*]] = extractelement <4 x i16> %data, i32 2 ; CHECK: [[DATA0_3:%.*]] = extractelement <4 x i16> %data, i32 3 ; CHECK: call void @dx.op.bufferStore.i16(i32 69, %dx.types.Handle [[HANDLE]], i32 %index, i32 undef, i16 [[DATA0_0]], i16 [[DATA0_1]], i16 [[DATA0_2]], i16 [[DATA0_3]], i8 15) - call void @llvm.dx.typedBufferStore( + call void @llvm.dx.resource.store.typedbuffer( target("dx.TypedBuffer", <4 x i16>, 1, 0, 0) %buffer, i32 %index, <4 x i16> %data) @@ -96,7 +96,7 @@ define void @store_scalarized_floats(float %data0, float %data1, float %data2, f ; CHECK: [[BIND:%.*]] = call %dx.types.Handle @dx.op.createHandleFromBinding(i32 217, ; CHECK: [[HANDLE:%.*]] = call %dx.types.Handle @dx.op.annotateHandle(i32 216, %dx.types.Handle [[BIND]] %buffer = call target("dx.TypedBuffer", <4 x float>, 1, 0, 0) - @llvm.dx.handle.fromBinding.tdx.TypedBuffer_v4f32_1_0_0( + @llvm.dx.resource.handlefrombinding.tdx.TypedBuffer_v4f32_1_0_0( i32 0, i32 0, i32 1, i32 0, i1 false) ; We shouldn't end up with any inserts/extracts. @@ -108,7 +108,7 @@ define void @store_scalarized_floats(float %data0, float %data1, float %data2, f %vec.upto1 = insertelement <4 x float> %vec.upto0, float %data1, i64 1 %vec.upto2 = insertelement <4 x float> %vec.upto1, float %data2, i64 2 %vec = insertelement <4 x float> %vec.upto2, float %data3, i64 3 - call void @llvm.dx.typedBufferStore( + call void @llvm.dx.resource.store.typedbuffer( target("dx.TypedBuffer", <4 x float>, 1, 0, 0) %buffer, i32 %index, <4 x float> %vec) diff --git a/llvm/test/CodeGen/DirectX/ContainerData/PSVResources.ll b/llvm/test/CodeGen/DirectX/ContainerData/PSVResources.ll index 2bd7a2e8df12db..ce67812c3988f1 100644 --- a/llvm/test/CodeGen/DirectX/ContainerData/PSVResources.ll +++ b/llvm/test/CodeGen/DirectX/ContainerData/PSVResources.ll @@ -15,7 +15,7 @@ define void @main() #0 { ; CHECK: Flags: ; CHECK: UsedByAtomic64: false %srv0 = call target("dx.RawBuffer", i8, 0, 0) - @llvm.dx.handle.fromBinding.tdx.RawBuffer_i8_0_0t( + @llvm.dx.resource.handlefrombinding.tdx.RawBuffer_i8_0_0t( i32 1, i32 8, i32 1, i32 0, i1 false) ; struct S { float4 a; uint4 b; }; @@ -28,7 +28,7 @@ define void @main() #0 { ; CHECK: Flags: ; CHECK: UsedByAtomic64: false %srv1 = call target("dx.RawBuffer", {<4 x float>, <4 x i32>}, 0, 0) - @llvm.dx.handle.fromBinding.tdx.RawBuffer_sl_v4f32v4i32s_0_0t( + @llvm.dx.resource.handlefrombinding.tdx.RawBuffer_sl_v4f32v4i32s_0_0t( i32 4, i32 2, i32 1, i32 0, i1 false) ; Buffer Buf[24] : register(t3, space5) @@ -40,7 +40,7 @@ define void @main() #0 { ; CHECK: Flags: ; CHECK: UsedByAtomic64: false %srv2 = call target("dx.TypedBuffer", <4 x i32>, 0, 0, 0) - @llvm.dx.handle.fromBinding.tdx.TypedBuffer_i32_0_0t( + @llvm.dx.resource.handlefrombinding.tdx.TypedBuffer_i32_0_0t( i32 5, i32 3, i32 24, i32 0, i1 false) ; RWBuffer Buf : register(u7, space2) @@ -52,7 +52,7 @@ define void @main() #0 { ; CHECK: Flags: ; CHECK: UsedByAtomic64: false %uav0 = call target("dx.TypedBuffer", i32, 1, 0, 1) - @llvm.dx.handle.fromBinding.tdx.TypedBuffer_i32_1_0t( + @llvm.dx.resource.handlefrombinding.tdx.TypedBuffer_i32_1_0t( i32 2, i32 7, i32 1, i32 0, i1 false) ; RWBuffer Buf : register(u5, space3) @@ -64,7 +64,7 @@ define void @main() #0 { ; CHECK: Flags: ; CHECK: UsedByAtomic64: false %uav1 = call target("dx.TypedBuffer", <4 x float>, 1, 0, 0) - @llvm.dx.handle.fromBinding.tdx.TypedBuffer_f32_1_0( + @llvm.dx.resource.handlefrombinding.tdx.TypedBuffer_f32_1_0( i32 3, i32 5, i32 1, i32 0, i1 false) ; RWBuffer BufferArray[10] : register(u0, space4) @@ -77,11 +77,11 @@ define void @main() #0 { ; CHECK: UsedByAtomic64: false ; RWBuffer Buf = BufferArray[0] %uav2_1 = call target("dx.TypedBuffer", <4 x float>, 1, 0, 0) - @llvm.dx.handle.fromBinding.tdx.TypedBuffer_f32_1_0( + @llvm.dx.resource.handlefrombinding.tdx.TypedBuffer_f32_1_0( i32 4, i32 0, i32 10, i32 0, i1 false) ; RWBuffer Buf = BufferArray[5] %uav2_2 = call target("dx.TypedBuffer", <4 x float>, 1, 0, 0) - @llvm.dx.handle.fromBinding.tdx.TypedBuffer_f32_1_0( + @llvm.dx.resource.handlefrombinding.tdx.TypedBuffer_f32_1_0( i32 4, i32 0, i32 10, i32 5, i1 false) ret void } diff --git a/llvm/test/CodeGen/DirectX/CreateHandle.ll b/llvm/test/CodeGen/DirectX/CreateHandle.ll index c9969c9c7ffdbf..80daa879f0f869 100644 --- a/llvm/test/CodeGen/DirectX/CreateHandle.ll +++ b/llvm/test/CodeGen/DirectX/CreateHandle.ll @@ -17,14 +17,14 @@ declare i32 @some_val(); define void @test_buffers() { ; RWBuffer Buf : register(u5, space3) %typed0 = call target("dx.TypedBuffer", <4 x float>, 1, 0, 0) - @llvm.dx.handle.fromBinding.tdx.TypedBuffer_v4f32_1_0_0( + @llvm.dx.resource.handlefrombinding.tdx.TypedBuffer_v4f32_1_0_0( i32 3, i32 5, i32 1, i32 0, i1 false) ; CHECK: call %dx.types.Handle @dx.op.createHandle(i32 57, i8 1, i32 1, i32 5, i1 false) ; CHECK-NOT: @llvm.dx.cast.handle ; RWBuffer Buf : register(u7, space2) %typed1 = call target("dx.TypedBuffer", i32, 1, 0, 1) - @llvm.dx.handle.fromBinding.tdx.TypedBuffer_i32_1_0_1t( + @llvm.dx.resource.handlefrombinding.tdx.TypedBuffer_i32_1_0_1t( i32 2, i32 7, i32 1, i32 0, i1 false) ; CHECK: call %dx.types.Handle @dx.op.createHandle(i32 57, i8 1, i32 0, i32 7, i1 false) @@ -32,20 +32,20 @@ define void @test_buffers() { ; Buffer typed2 = Buf[4] ; Note that the index below is 3 + 4 = 7 %typed2 = call target("dx.TypedBuffer", <4 x i32>, 0, 0, 0) - @llvm.dx.handle.fromBinding.tdx.TypedBuffer_i32_0_0_0t( + @llvm.dx.resource.handlefrombinding.tdx.TypedBuffer_i32_0_0_0t( i32 5, i32 3, i32 24, i32 4, i1 false) ; CHECK: call %dx.types.Handle @dx.op.createHandle(i32 57, i8 0, i32 3, i32 7, i1 false) ; struct S { float4 a; uint4 b; }; ; StructuredBuffer Buf : register(t2, space4) %struct0 = call target("dx.RawBuffer", {<4 x float>, <4 x i32>}, 0, 0) - @llvm.dx.handle.fromBinding.tdx.RawBuffer_sl_v4f32v4i32s_0_0t( + @llvm.dx.resource.handlefrombinding.tdx.RawBuffer_sl_v4f32v4i32s_0_0t( i32 4, i32 2, i32 1, i32 0, i1 true) ; CHECK: call %dx.types.Handle @dx.op.createHandle(i32 57, i8 0, i32 2, i32 2, i1 true) ; ByteAddressBuffer Buf : register(t8, space1) %byteaddr0 = call target("dx.RawBuffer", i8, 0, 0) - @llvm.dx.handle.fromBinding.tdx.RawBuffer_i8_0_0t( + @llvm.dx.resource.handlefrombinding.tdx.RawBuffer_i8_0_0t( i32 1, i32 8, i32 1, i32 0, i1 false) ; CHECK: call %dx.types.Handle @dx.op.createHandle(i32 57, i8 0, i32 1, i32 8, i1 false) @@ -53,7 +53,7 @@ define void @test_buffers() { ; Buffer typed3 = Buf[ix] %typed3_ix = call i32 @some_val() %typed3 = call target("dx.TypedBuffer", <4 x float>, 0, 0, 0) - @llvm.dx.handle.fromBinding.tdx.TypedBuffer_v4f32_0_0_0t( + @llvm.dx.resource.handlefrombinding.tdx.TypedBuffer_v4f32_0_0_0t( i32 0, i32 7, i32 -1, i32 %typed3_ix, i1 false) ; CHECK: %[[IX:.*]] = add i32 %typed3_ix, 7 ; CHECK: call %dx.types.Handle @dx.op.createHandle(i32 57, i8 0, i32 0, i32 %[[IX]], i1 false) diff --git a/llvm/test/CodeGen/DirectX/CreateHandleFromBinding.ll b/llvm/test/CodeGen/DirectX/CreateHandleFromBinding.ll index 425084e2a65a97..bf11bfa143c936 100644 --- a/llvm/test/CodeGen/DirectX/CreateHandleFromBinding.ll +++ b/llvm/test/CodeGen/DirectX/CreateHandleFromBinding.ll @@ -17,14 +17,14 @@ declare i32 @some_val(); define void @test_bindings() { ; RWBuffer Buf : register(u5, space3) %typed0 = call target("dx.TypedBuffer", <4 x float>, 1, 0, 0) - @llvm.dx.handle.fromBinding.tdx.TypedBuffer_v4f32_1_0_0( + @llvm.dx.resource.handlefrombinding.tdx.TypedBuffer_v4f32_1_0_0( i32 3, i32 5, i32 1, i32 0, i1 false) ; CHECK: [[BUF0:%.*]] = call %dx.types.Handle @dx.op.createHandleFromBinding(i32 217, %dx.types.ResBind { i32 5, i32 5, i32 3, i8 1 }, i32 5, i1 false) ; CHECK: call %dx.types.Handle @dx.op.annotateHandle(i32 216, %dx.types.Handle [[BUF0]], %dx.types.ResourceProperties { i32 4106, i32 1033 }) ; RWBuffer Buf : register(u7, space2) %typed1 = call target("dx.TypedBuffer", i32, 1, 0, 1) - @llvm.dx.handle.fromBinding.tdx.TypedBuffer_i32_1_0_0t( + @llvm.dx.resource.handlefrombinding.tdx.TypedBuffer_i32_1_0_0t( i32 2, i32 7, i32 1, i32 0, i1 false) ; CHECK: [[BUF1:%.*]] = call %dx.types.Handle @dx.op.createHandleFromBinding(i32 217, %dx.types.ResBind { i32 7, i32 7, i32 2, i8 1 }, i32 7, i1 false) ; CHECK: call %dx.types.Handle @dx.op.annotateHandle(i32 216, %dx.types.Handle [[BUF1]], %dx.types.ResourceProperties { i32 4106, i32 260 }) @@ -33,7 +33,7 @@ define void @test_bindings() { ; Buffer typed2 = Buf[4] ; Note that the index below is 3 + 4 = 7 %typed2 = call target("dx.TypedBuffer", <4 x i32>, 0, 0, 0) - @llvm.dx.handle.fromBinding.tdx.TypedBuffer_i32_0_0_0t( + @llvm.dx.resource.handlefrombinding.tdx.TypedBuffer_i32_0_0_0t( i32 5, i32 3, i32 24, i32 4, i1 false) ; CHECK: [[BUF2:%.*]] = call %dx.types.Handle @dx.op.createHandleFromBinding(i32 217, %dx.types.ResBind { i32 3, i32 26, i32 5, i8 0 }, i32 7, i1 false) ; CHECK: call %dx.types.Handle @dx.op.annotateHandle(i32 216, %dx.types.Handle [[BUF2]], %dx.types.ResourceProperties { i32 10, i32 1029 }) @@ -41,14 +41,14 @@ define void @test_bindings() { ; struct S { float4 a; uint4 b; }; ; StructuredBuffer Buf : register(t2, space4) %struct0 = call target("dx.RawBuffer", {<4 x float>, <4 x i32>}, 0, 0) - @llvm.dx.handle.fromBinding.tdx.RawBuffer_sl_v4f32v4i32s_0_0t( + @llvm.dx.resource.handlefrombinding.tdx.RawBuffer_sl_v4f32v4i32s_0_0t( i32 4, i32 2, i32 1, i32 0, i1 true) ; CHECK: [[BUF3:%.*]] = call %dx.types.Handle @dx.op.createHandleFromBinding(i32 217, %dx.types.ResBind { i32 2, i32 2, i32 4, i8 0 }, i32 2, i1 true) ; CHECK: = call %dx.types.Handle @dx.op.annotateHandle(i32 216, %dx.types.Handle [[BUF3]], %dx.types.ResourceProperties { i32 1036, i32 32 }) ; ByteAddressBuffer Buf : register(t8, space1) %byteaddr0 = call target("dx.RawBuffer", i8, 0, 0) - @llvm.dx.handle.fromBinding.tdx.RawBuffer_i8_0_0t( + @llvm.dx.resource.handlefrombinding.tdx.RawBuffer_i8_0_0t( i32 1, i32 8, i32 1, i32 0, i1 false) ; CHECK: [[BUF4:%.*]] = call %dx.types.Handle @dx.op.createHandleFromBinding(i32 217, %dx.types.ResBind { i32 8, i32 8, i32 1, i8 0 }, i32 8, i1 false) ; CHECK: call %dx.types.Handle @dx.op.annotateHandle(i32 216, %dx.types.Handle [[BUF4]], %dx.types.ResourceProperties { i32 11, i32 0 }) @@ -57,7 +57,7 @@ define void @test_bindings() { ; Buffer typed3 = Buf[ix] %typed3_ix = call i32 @some_val() %typed3 = call target("dx.TypedBuffer", <4 x float>, 0, 0, 0) - @llvm.dx.handle.fromBinding.tdx.TypedBuffer_v4f32_0_0_0t( + @llvm.dx.resource.handlefrombinding.tdx.TypedBuffer_v4f32_0_0_0t( i32 0, i32 7, i32 -1, i32 %typed3_ix, i1 false) ; CHECK: %[[IX:.*]] = add i32 %typed3_ix, 7 ; CHECK: [[BUF5:%.*]] = call %dx.types.Handle @dx.op.createHandleFromBinding(i32 217, %dx.types.ResBind { i32 7, i32 -1, i32 0, i8 0 }, i32 %[[IX]], i1 false) diff --git a/llvm/test/CodeGen/DirectX/Metadata/resource-symbols.ll b/llvm/test/CodeGen/DirectX/Metadata/resource-symbols.ll index 5ac4baa96c6599..6ebe4b5eb23a59 100644 --- a/llvm/test/CodeGen/DirectX/Metadata/resource-symbols.ll +++ b/llvm/test/CodeGen/DirectX/Metadata/resource-symbols.ll @@ -7,27 +7,27 @@ target triple = "dxil-pc-shadermodel6.6-compute" define void @test() { ; Buffer %float4 = call target("dx.TypedBuffer", <4 x float>, 0, 0, 0) - @llvm.dx.handle.fromBinding(i32 0, i32 0, i32 1, i32 0, i1 false) + @llvm.dx.resource.handlefrombinding(i32 0, i32 0, i32 1, i32 0, i1 false) ; CHECK: %TypedBuffer = type { <4 x float> } ; Buffer %int = call target("dx.TypedBuffer", i32, 0, 0, 1) - @llvm.dx.handle.fromBinding(i32 0, i32 1, i32 1, i32 0, i1 false) + @llvm.dx.resource.handlefrombinding(i32 0, i32 1, i32 1, i32 0, i1 false) ; CHECK: %TypedBuffer.0 = type { i32 } ; Buffer %uint3 = call target("dx.TypedBuffer", <3 x i32>, 0, 0, 0) - @llvm.dx.handle.fromBinding(i32 0, i32 2, i32 1, i32 0, i1 false) + @llvm.dx.resource.handlefrombinding(i32 0, i32 2, i32 1, i32 0, i1 false) ; CHECK: %TypedBuffer.1 = type { <3 x i32> } ; StructuredBuffer %struct0 = call target("dx.RawBuffer", %struct.S, 0, 0) - @llvm.dx.handle.fromBinding(i32 0, i32 10, i32 1, i32 0, i1 true) + @llvm.dx.resource.handlefrombinding(i32 0, i32 10, i32 1, i32 0, i1 true) ; CHECK: %StructuredBuffer = type { %struct.S } ; ByteAddressBuffer %byteaddr = call target("dx.RawBuffer", i8, 0, 0) - @llvm.dx.handle.fromBinding(i32 0, i32 20, i32 1, i32 0, i1 false) + @llvm.dx.resource.handlefrombinding(i32 0, i32 20, i32 1, i32 0, i1 false) ; CHECK: %ByteAddressBuffer = type { i32 } ret void diff --git a/llvm/test/CodeGen/DirectX/ResourceAccess/load_typedbuffer.ll b/llvm/test/CodeGen/DirectX/ResourceAccess/load_typedbuffer.ll index a40e6cbc6fa4ff..9b7e7fd04f6052 100644 --- a/llvm/test/CodeGen/DirectX/ResourceAccess/load_typedbuffer.ll +++ b/llvm/test/CodeGen/DirectX/ResourceAccess/load_typedbuffer.ll @@ -8,24 +8,24 @@ declare void @use_float(float) ; CHECK-LABEL: define void @load_float4 define void @load_float4(i32 %index, i32 %elemindex) { %buffer = call target("dx.TypedBuffer", <4 x float>, 1, 0, 0) - @llvm.dx.handle.fromBinding.tdx.TypedBuffer_v4f32_1_0_0( + @llvm.dx.resource.handlefrombinding.tdx.TypedBuffer_v4f32_1_0_0( i32 0, i32 0, i32 1, i32 0, i1 false) ; CHECK-NOT: @llvm.dx.resource.getpointer %ptr = call ptr @llvm.dx.resource.getpointer( target("dx.TypedBuffer", <4 x float>, 1, 0, 0) %buffer, i32 %index) - ; CHECK: %[[VALUE:.*]] = call <4 x float> @llvm.dx.typedBufferLoad.v4f32.tdx.TypedBuffer_v4f32_1_0_0t(target("dx.TypedBuffer", <4 x float>, 1, 0, 0) %buffer, i32 %index) + ; CHECK: %[[VALUE:.*]] = call <4 x float> @llvm.dx.resource.load.typedbuffer.v4f32.tdx.TypedBuffer_v4f32_1_0_0t(target("dx.TypedBuffer", <4 x float>, 1, 0, 0) %buffer, i32 %index) %vec_data = load <4 x float>, ptr %ptr call void @use_float4(<4 x float> %vec_data) - ; CHECK: %[[VALUE:.*]] = call <4 x float> @llvm.dx.typedBufferLoad.v4f32.tdx.TypedBuffer_v4f32_1_0_0t(target("dx.TypedBuffer", <4 x float>, 1, 0, 0) %buffer, i32 %index) + ; CHECK: %[[VALUE:.*]] = call <4 x float> @llvm.dx.resource.load.typedbuffer.v4f32.tdx.TypedBuffer_v4f32_1_0_0t(target("dx.TypedBuffer", <4 x float>, 1, 0, 0) %buffer, i32 %index) ; CHECK: extractelement <4 x float> %[[VALUE]], i32 1 %y_ptr = getelementptr inbounds <4 x float>, ptr %ptr, i32 0, i32 1 %y_data = load float, ptr %y_ptr call void @use_float(float %y_data) - ; CHECK: %[[VALUE:.*]] = call <4 x float> @llvm.dx.typedBufferLoad.v4f32.tdx.TypedBuffer_v4f32_1_0_0t(target("dx.TypedBuffer", <4 x float>, 1, 0, 0) %buffer, i32 %index) + ; CHECK: %[[VALUE:.*]] = call <4 x float> @llvm.dx.resource.load.typedbuffer.v4f32.tdx.TypedBuffer_v4f32_1_0_0t(target("dx.TypedBuffer", <4 x float>, 1, 0, 0) %buffer, i32 %index) ; CHECK: extractelement <4 x float> %[[VALUE]], i32 %elemindex %dynamic = getelementptr inbounds <4 x float>, ptr %ptr, i32 0, i32 %elemindex %dyndata = load float, ptr %dynamic diff --git a/llvm/test/CodeGen/DirectX/ResourceAccess/store_typedbuffer.ll b/llvm/test/CodeGen/DirectX/ResourceAccess/store_typedbuffer.ll index dd63acc3c0e96c..17606408cadfff 100644 --- a/llvm/test/CodeGen/DirectX/ResourceAccess/store_typedbuffer.ll +++ b/llvm/test/CodeGen/DirectX/ResourceAccess/store_typedbuffer.ll @@ -5,7 +5,7 @@ target triple = "dxil-pc-shadermodel6.6-compute" ; CHECK-LABEL: define void @store_float4 define void @store_float4(<4 x float> %data, i32 %index, i32 %elemindex) { %buffer = call target("dx.TypedBuffer", <4 x float>, 1, 0, 0) - @llvm.dx.handle.fromBinding.tdx.TypedBuffer_v4f32_1_0_0( + @llvm.dx.resource.handlefrombinding.tdx.TypedBuffer_v4f32_1_0_0( i32 0, i32 0, i32 1, i32 0, i1 false) ; CHECK-NOT: @llvm.dx.resource.getpointer @@ -13,27 +13,27 @@ define void @store_float4(<4 x float> %data, i32 %index, i32 %elemindex) { target("dx.TypedBuffer", <4 x float>, 1, 0, 0) %buffer, i32 %index) ; Store the whole value - ; CHECK: call void @llvm.dx.typedBufferStore.tdx.TypedBuffer_v4f32_1_0_0t.v4f32(target("dx.TypedBuffer", <4 x float>, 1, 0, 0) %buffer, i32 %index, <4 x float> %data) + ; CHECK: call void @llvm.dx.resource.store.typedbuffer.tdx.TypedBuffer_v4f32_1_0_0t.v4f32(target("dx.TypedBuffer", <4 x float>, 1, 0, 0) %buffer, i32 %index, <4 x float> %data) store <4 x float> %data, ptr %ptr ; Store just the .x component %scalar = extractelement <4 x float> %data, i32 0 - ; CHECK: %[[LOAD:.*]] = call <4 x float> @llvm.dx.typedBufferLoad.v4f32.tdx.TypedBuffer_v4f32_1_0_0t(target("dx.TypedBuffer", <4 x float>, 1, 0, 0) %buffer, i32 %index) + ; CHECK: %[[LOAD:.*]] = call <4 x float> @llvm.dx.resource.load.typedbuffer.v4f32.tdx.TypedBuffer_v4f32_1_0_0t(target("dx.TypedBuffer", <4 x float>, 1, 0, 0) %buffer, i32 %index) ; CHECK: %[[INSERT:.*]] = insertelement <4 x float> %[[LOAD]], float %scalar, i32 0 - ; CHECK: call void @llvm.dx.typedBufferStore.tdx.TypedBuffer_v4f32_1_0_0t.v4f32(target("dx.TypedBuffer", <4 x float>, 1, 0, 0) %buffer, i32 %index, <4 x float> %[[INSERT]]) + ; CHECK: call void @llvm.dx.resource.store.typedbuffer.tdx.TypedBuffer_v4f32_1_0_0t.v4f32(target("dx.TypedBuffer", <4 x float>, 1, 0, 0) %buffer, i32 %index, <4 x float> %[[INSERT]]) store float %scalar, ptr %ptr ; Store just the .y component - ; CHECK: %[[LOAD:.*]] = call <4 x float> @llvm.dx.typedBufferLoad.v4f32.tdx.TypedBuffer_v4f32_1_0_0t(target("dx.TypedBuffer", <4 x float>, 1, 0, 0) %buffer, i32 %index) + ; CHECK: %[[LOAD:.*]] = call <4 x float> @llvm.dx.resource.load.typedbuffer.v4f32.tdx.TypedBuffer_v4f32_1_0_0t(target("dx.TypedBuffer", <4 x float>, 1, 0, 0) %buffer, i32 %index) ; CHECK: %[[INSERT:.*]] = insertelement <4 x float> %[[LOAD]], float %scalar, i32 1 - ; CHECK: call void @llvm.dx.typedBufferStore.tdx.TypedBuffer_v4f32_1_0_0t.v4f32(target("dx.TypedBuffer", <4 x float>, 1, 0, 0) %buffer, i32 %index, <4 x float> %[[INSERT]]) + ; CHECK: call void @llvm.dx.resource.store.typedbuffer.tdx.TypedBuffer_v4f32_1_0_0t.v4f32(target("dx.TypedBuffer", <4 x float>, 1, 0, 0) %buffer, i32 %index, <4 x float> %[[INSERT]]) %y_ptr = getelementptr inbounds i8, ptr %ptr, i32 4 store float %scalar, ptr %y_ptr ; Store to one of the elements dynamically - ; CHECK: %[[LOAD:.*]] = call <4 x float> @llvm.dx.typedBufferLoad.v4f32.tdx.TypedBuffer_v4f32_1_0_0t(target("dx.TypedBuffer", <4 x float>, 1, 0, 0) %buffer, i32 %index) + ; CHECK: %[[LOAD:.*]] = call <4 x float> @llvm.dx.resource.load.typedbuffer.v4f32.tdx.TypedBuffer_v4f32_1_0_0t(target("dx.TypedBuffer", <4 x float>, 1, 0, 0) %buffer, i32 %index) ; CHECK: %[[INSERT:.*]] = insertelement <4 x float> %[[LOAD]], float %scalar, i32 %elemindex - ; CHECK: call void @llvm.dx.typedBufferStore.tdx.TypedBuffer_v4f32_1_0_0t.v4f32(target("dx.TypedBuffer", <4 x float>, 1, 0, 0) %buffer, i32 %index, <4 x float> %[[INSERT]]) + ; CHECK: call void @llvm.dx.resource.store.typedbuffer.tdx.TypedBuffer_v4f32_1_0_0t.v4f32(target("dx.TypedBuffer", <4 x float>, 1, 0, 0) %buffer, i32 %index, <4 x float> %[[INSERT]]) %dynamic = getelementptr inbounds <4 x float>, ptr %ptr, i32 0, i32 %elemindex store float %scalar, ptr %dynamic @@ -43,7 +43,7 @@ define void @store_float4(<4 x float> %data, i32 %index, i32 %elemindex) { ; CHECK-LABEL: define void @store_half4 define void @store_half4(<4 x half> %data, i32 %index) { %buffer = call target("dx.TypedBuffer", <4 x half>, 1, 0, 0) - @llvm.dx.handle.fromBinding.tdx.TypedBuffer_v4f16_1_0_0( + @llvm.dx.resource.handlefrombinding.tdx.TypedBuffer_v4f16_1_0_0( i32 0, i32 0, i32 1, i32 0, i1 false) ; CHECK-NOT: @llvm.dx.resource.getpointer @@ -51,20 +51,20 @@ define void @store_half4(<4 x half> %data, i32 %index) { target("dx.TypedBuffer", <4 x half>, 1, 0, 0) %buffer, i32 %index) ; Store the whole value - ; CHECK: call void @llvm.dx.typedBufferStore.tdx.TypedBuffer_v4f16_1_0_0t.v4f16(target("dx.TypedBuffer", <4 x half>, 1, 0, 0) %buffer, i32 %index, <4 x half> %data) + ; CHECK: call void @llvm.dx.resource.store.typedbuffer.tdx.TypedBuffer_v4f16_1_0_0t.v4f16(target("dx.TypedBuffer", <4 x half>, 1, 0, 0) %buffer, i32 %index, <4 x half> %data) store <4 x half> %data, ptr %ptr ; Store just the .x component %scalar = extractelement <4 x half> %data, i32 0 - ; CHECK: %[[LOAD:.*]] = call <4 x half> @llvm.dx.typedBufferLoad.v4f16.tdx.TypedBuffer_v4f16_1_0_0t(target("dx.TypedBuffer", <4 x half>, 1, 0, 0) %buffer, i32 %index) + ; CHECK: %[[LOAD:.*]] = call <4 x half> @llvm.dx.resource.load.typedbuffer.v4f16.tdx.TypedBuffer_v4f16_1_0_0t(target("dx.TypedBuffer", <4 x half>, 1, 0, 0) %buffer, i32 %index) ; CHECK: %[[INSERT:.*]] = insertelement <4 x half> %[[LOAD]], half %scalar, i32 0 - ; CHECK: call void @llvm.dx.typedBufferStore.tdx.TypedBuffer_v4f16_1_0_0t.v4f16(target("dx.TypedBuffer", <4 x half>, 1, 0, 0) %buffer, i32 %index, <4 x half> %[[INSERT]]) + ; CHECK: call void @llvm.dx.resource.store.typedbuffer.tdx.TypedBuffer_v4f16_1_0_0t.v4f16(target("dx.TypedBuffer", <4 x half>, 1, 0, 0) %buffer, i32 %index, <4 x half> %[[INSERT]]) store half %scalar, ptr %ptr ; Store just the .y component - ; CHECK: %[[LOAD:.*]] = call <4 x half> @llvm.dx.typedBufferLoad.v4f16.tdx.TypedBuffer_v4f16_1_0_0t(target("dx.TypedBuffer", <4 x half>, 1, 0, 0) %buffer, i32 %index) + ; CHECK: %[[LOAD:.*]] = call <4 x half> @llvm.dx.resource.load.typedbuffer.v4f16.tdx.TypedBuffer_v4f16_1_0_0t(target("dx.TypedBuffer", <4 x half>, 1, 0, 0) %buffer, i32 %index) ; CHECK: %[[INSERT:.*]] = insertelement <4 x half> %[[LOAD]], half %scalar, i32 1 - ; CHECK: call void @llvm.dx.typedBufferStore.tdx.TypedBuffer_v4f16_1_0_0t.v4f16(target("dx.TypedBuffer", <4 x half>, 1, 0, 0) %buffer, i32 %index, <4 x half> %[[INSERT]]) + ; CHECK: call void @llvm.dx.resource.store.typedbuffer.tdx.TypedBuffer_v4f16_1_0_0t.v4f16(target("dx.TypedBuffer", <4 x half>, 1, 0, 0) %buffer, i32 %index, <4 x half> %[[INSERT]]) %y_ptr = getelementptr inbounds i8, ptr %ptr, i32 2 store half %scalar, ptr %y_ptr @@ -74,7 +74,7 @@ define void @store_half4(<4 x half> %data, i32 %index) { ; CHECK-LABEL: define void @store_double2 define void @store_double2(<2 x double> %data, i32 %index) { %buffer = call target("dx.TypedBuffer", <2 x double>, 1, 0, 0) - @llvm.dx.handle.fromBinding.tdx.TypedBuffer_v2f64_1_0_0( + @llvm.dx.resource.handlefrombinding.tdx.TypedBuffer_v2f64_1_0_0( i32 0, i32 0, i32 1, i32 0, i1 false) ; CHECK-NOT: @llvm.dx.resource.getpointer @@ -82,20 +82,20 @@ define void @store_double2(<2 x double> %data, i32 %index) { target("dx.TypedBuffer", <2 x double>, 1, 0, 0) %buffer, i32 %index) ; Store the whole value - ; CHECK: call void @llvm.dx.typedBufferStore.tdx.TypedBuffer_v2f64_1_0_0t.v2f64(target("dx.TypedBuffer", <2 x double>, 1, 0, 0) %buffer, i32 %index, <2 x double> %data) + ; CHECK: call void @llvm.dx.resource.store.typedbuffer.tdx.TypedBuffer_v2f64_1_0_0t.v2f64(target("dx.TypedBuffer", <2 x double>, 1, 0, 0) %buffer, i32 %index, <2 x double> %data) store <2 x double> %data, ptr %ptr ; Store just the .x component %scalar = extractelement <2 x double> %data, i32 0 - ; CHECK: %[[LOAD:.*]] = call <2 x double> @llvm.dx.typedBufferLoad.v2f64.tdx.TypedBuffer_v2f64_1_0_0t(target("dx.TypedBuffer", <2 x double>, 1, 0, 0) %buffer, i32 %index) + ; CHECK: %[[LOAD:.*]] = call <2 x double> @llvm.dx.resource.load.typedbuffer.v2f64.tdx.TypedBuffer_v2f64_1_0_0t(target("dx.TypedBuffer", <2 x double>, 1, 0, 0) %buffer, i32 %index) ; CHECK: %[[INSERT:.*]] = insertelement <2 x double> %[[LOAD]], double %scalar, i32 0 - ; CHECK: call void @llvm.dx.typedBufferStore.tdx.TypedBuffer_v2f64_1_0_0t.v2f64(target("dx.TypedBuffer", <2 x double>, 1, 0, 0) %buffer, i32 %index, <2 x double> %[[INSERT]]) + ; CHECK: call void @llvm.dx.resource.store.typedbuffer.tdx.TypedBuffer_v2f64_1_0_0t.v2f64(target("dx.TypedBuffer", <2 x double>, 1, 0, 0) %buffer, i32 %index, <2 x double> %[[INSERT]]) store double %scalar, ptr %ptr ; Store just the .y component - ; CHECK: %[[LOAD:.*]] = call <2 x double> @llvm.dx.typedBufferLoad.v2f64.tdx.TypedBuffer_v2f64_1_0_0t(target("dx.TypedBuffer", <2 x double>, 1, 0, 0) %buffer, i32 %index) + ; CHECK: %[[LOAD:.*]] = call <2 x double> @llvm.dx.resource.load.typedbuffer.v2f64.tdx.TypedBuffer_v2f64_1_0_0t(target("dx.TypedBuffer", <2 x double>, 1, 0, 0) %buffer, i32 %index) ; CHECK: %[[INSERT:.*]] = insertelement <2 x double> %[[LOAD]], double %scalar, i32 1 - ; CHECK: call void @llvm.dx.typedBufferStore.tdx.TypedBuffer_v2f64_1_0_0t.v2f64(target("dx.TypedBuffer", <2 x double>, 1, 0, 0) %buffer, i32 %index, <2 x double> %[[INSERT]]) + ; CHECK: call void @llvm.dx.resource.store.typedbuffer.tdx.TypedBuffer_v2f64_1_0_0t.v2f64(target("dx.TypedBuffer", <2 x double>, 1, 0, 0) %buffer, i32 %index, <2 x double> %[[INSERT]]) %y_ptr = getelementptr inbounds i8, ptr %ptr, i32 8 store double %scalar, ptr %y_ptr diff --git a/llvm/test/CodeGen/DirectX/ResourceGlobalElimination.ll b/llvm/test/CodeGen/DirectX/ResourceGlobalElimination.ll index c0fbc3d9150bc7..c837b36a19e119 100644 --- a/llvm/test/CodeGen/DirectX/ResourceGlobalElimination.ll +++ b/llvm/test/CodeGen/DirectX/ResourceGlobalElimination.ll @@ -21,27 +21,27 @@ define void @main() local_unnamed_addr #0 { entry: ; DXOP: %In_h.i1 = call %dx.types.Handle @dx.op.createHandle ; DXOP: %Out_h.i2 = call %dx.types.Handle @dx.op.createHandle - %In_h.i = call target("dx.TypedBuffer", <4 x float>, 1, 0, 0) @llvm.dx.handle.fromBinding.tdx.TypedBuffer_v4f32_1_0_0t(i32 0, i32 0, i32 1, i32 0, i1 false) + %In_h.i = call target("dx.TypedBuffer", <4 x float>, 1, 0, 0) @llvm.dx.resource.handlefrombinding.tdx.TypedBuffer_v4f32_1_0_0t(i32 0, i32 0, i32 1, i32 0, i1 false) store target("dx.TypedBuffer", <4 x float>, 1, 0, 0) %In_h.i, ptr @In, align 4 - %Out_h.i = call target("dx.TypedBuffer", <4 x float>, 1, 0, 0) @llvm.dx.handle.fromBinding.tdx.TypedBuffer_v4f32_1_0_0t(i32 4, i32 1, i32 1, i32 0, i1 false) + %Out_h.i = call target("dx.TypedBuffer", <4 x float>, 1, 0, 0) @llvm.dx.resource.handlefrombinding.tdx.TypedBuffer_v4f32_1_0_0t(i32 4, i32 1, i32 1, i32 0, i1 false) store target("dx.TypedBuffer", <4 x float>, 1, 0, 0) %Out_h.i, ptr @Out, align 4 ; CSE: call i32 @llvm.dx.flattened.thread.id.in.group() %0 = call i32 @llvm.dx.flattened.thread.id.in.group() ; CHECK-NOT: load {{.*}} ptr @In %1 = load target("dx.TypedBuffer", <4 x float>, 1, 0, 0), ptr @In, align 4 - ; CSE: call noundef <4 x float> @llvm.dx.typedBufferLoad.v4f32.tdx.TypedBuffer_v4f32_1_0_0t - %2 = call noundef <4 x float> @llvm.dx.typedBufferLoad.v4f32.tdx.TypedBuffer_v4f32_1_0_0t(target("dx.TypedBuffer", <4 x float>, 1, 0, 0) %1, i32 %0) + ; CSE: call noundef <4 x float> @llvm.dx.resource.load.typedbuffer.v4f32.tdx.TypedBuffer_v4f32_1_0_0t + %2 = call noundef <4 x float> @llvm.dx.resource.load.typedbuffer.v4f32.tdx.TypedBuffer_v4f32_1_0_0t(target("dx.TypedBuffer", <4 x float>, 1, 0, 0) %1, i32 %0) ; CHECK-NOT: load {{.*}} ptr @In %3 = load target("dx.TypedBuffer", <4 x float>, 1, 0, 0), ptr @In, align 4 - %4 = call noundef <4 x float> @llvm.dx.typedBufferLoad.v4f32.tdx.TypedBuffer_v4f32_1_0_0t(target("dx.TypedBuffer", <4 x float>, 1, 0, 0) %3, i32 %0) + %4 = call noundef <4 x float> @llvm.dx.resource.load.typedbuffer.v4f32.tdx.TypedBuffer_v4f32_1_0_0t(target("dx.TypedBuffer", <4 x float>, 1, 0, 0) %3, i32 %0) %add.i = fadd <4 x float> %2, %4 - call void @llvm.dx.typedBufferStore.tdx.TypedBuffer_v4f32_1_0_0t.v4f32(target("dx.TypedBuffer", <4 x float>, 1, 0, 0) %Out_h.i, i32 %0, <4 x float> %add.i) + call void @llvm.dx.resource.store.typedbuffer.tdx.TypedBuffer_v4f32_1_0_0t.v4f32(target("dx.TypedBuffer", <4 x float>, 1, 0, 0) %Out_h.i, i32 %0, <4 x float> %add.i) ; CHECK: ret void ret void } -; CSE-DAG: declare <4 x float> @llvm.dx.typedBufferLoad.v4f32.tdx.TypedBuffer_v4f32_1_0_0t(target("dx.TypedBuffer", <4 x float>, 1, 0, 0), i32) [[ROAttr:#[0-9]+]] -; CSE-DAG: declare void @llvm.dx.typedBufferStore.tdx.TypedBuffer_v4f32_1_0_0t.v4f32(target("dx.TypedBuffer", <4 x float>, 1, 0, 0), i32, <4 x float>) [[WOAttr:#[0-9]+]] +; CSE-DAG: declare <4 x float> @llvm.dx.resource.load.typedbuffer.v4f32.tdx.TypedBuffer_v4f32_1_0_0t(target("dx.TypedBuffer", <4 x float>, 1, 0, 0), i32) [[ROAttr:#[0-9]+]] +; CSE-DAG: declare void @llvm.dx.resource.store.typedbuffer.tdx.TypedBuffer_v4f32_1_0_0t.v4f32(target("dx.TypedBuffer", <4 x float>, 1, 0, 0), i32, <4 x float>) [[WOAttr:#[0-9]+]] attributes #0 = { convergent noinline norecurse "frame-pointer"="all" "hlsl.numthreads"="8,1,1" "hlsl.shader"="compute" "no-trapping-math"="true" "stack-protector-buffer-size"="8" } diff --git a/llvm/test/CodeGen/DirectX/ShaderFlags/typed-uav-load-additional-formats.ll b/llvm/test/CodeGen/DirectX/ShaderFlags/typed-uav-load-additional-formats.ll index b6947393c4533d..26223359dfdf1c 100644 --- a/llvm/test/CodeGen/DirectX/ShaderFlags/typed-uav-load-additional-formats.ll +++ b/llvm/test/CodeGen/DirectX/ShaderFlags/typed-uav-load-additional-formats.ll @@ -16,8 +16,8 @@ target triple = "dxil-pc-shadermodel6.7-library" ; CHECK: Function multicomponent : 0x00002000 define <4 x float> @multicomponent() #0 { %res = call target("dx.TypedBuffer", <4 x float>, 1, 0, 0) - @llvm.dx.handle.fromBinding(i32 0, i32 0, i32 1, i32 0, i1 false) - %val = call <4 x float> @llvm.dx.typedBufferLoad( + @llvm.dx.resource.handlefrombinding(i32 0, i32 0, i32 1, i32 0, i1 false) + %val = call <4 x float> @llvm.dx.resource.load.typedbuffer( target("dx.TypedBuffer", <4 x float>, 1, 0, 0) %res, i32 0) ret <4 x float> %val } @@ -25,8 +25,8 @@ define <4 x float> @multicomponent() #0 { ; CHECK: Function onecomponent : 0x00000000 define float @onecomponent() #0 { %res = call target("dx.TypedBuffer", float, 1, 0, 0) - @llvm.dx.handle.fromBinding(i32 0, i32 0, i32 1, i32 0, i1 false) - %val = call float @llvm.dx.typedBufferLoad( + @llvm.dx.resource.handlefrombinding(i32 0, i32 0, i32 1, i32 0, i1 false) + %val = call float @llvm.dx.resource.load.typedbuffer( target("dx.TypedBuffer", float, 1, 0, 0) %res, i32 0) ret float %val } @@ -34,8 +34,8 @@ define float @onecomponent() #0 { ; CHECK: Function noload : 0x00000000 define void @noload(<4 x float> %val) #0 { %res = call target("dx.TypedBuffer", <4 x float>, 1, 0, 0) - @llvm.dx.handle.fromBinding(i32 0, i32 0, i32 1, i32 0, i1 false) - call void @llvm.dx.typedBufferStore( + @llvm.dx.resource.handlefrombinding(i32 0, i32 0, i32 1, i32 0, i1 false) + call void @llvm.dx.resource.store.typedbuffer( target("dx.TypedBuffer", <4 x float>, 1, 0, 0) %res, i32 0, <4 x float> %val) ret void diff --git a/llvm/test/CodeGen/DirectX/bufferUpdateCounter.ll b/llvm/test/CodeGen/DirectX/bufferUpdateCounter.ll index 3f2610649cba17..57a47d0a39a7cf 100644 --- a/llvm/test/CodeGen/DirectX/bufferUpdateCounter.ll +++ b/llvm/test/CodeGen/DirectX/bufferUpdateCounter.ll @@ -7,12 +7,12 @@ target triple = "dxil-pc-shadermodel6.6-compute" define void @update_counter_decrement_vector() { ; CHECK: [[BIND:%.*]] = call %dx.types.Handle @dx.op.createHandleFromBinding(i32 217, %buffer = call target("dx.TypedBuffer", <4 x float>, 0, 0, 0) - @llvm.dx.handle.fromBinding.tdx.TypedBuffer_v4f32_0_0_0( + @llvm.dx.resource.handlefrombinding.tdx.TypedBuffer_v4f32_0_0_0( i32 0, i32 0, i32 1, i32 0, i1 false) ; CHECK-NEXT: [[BUFFANOT:%.*]] = call %dx.types.Handle @dx.op.annotateHandle(i32 216, %dx.types.Handle [[BIND]] ; CHECK-NEXT: [[REG:%.*]] = call i32 @dx.op.bufferUpdateCounter(i32 70, %dx.types.Handle [[BUFFANOT]], i8 -1) - %1 = call i32 @llvm.dx.bufferUpdateCounter(target("dx.TypedBuffer", <4 x float>, 0, 0, 0) %buffer, i8 -1) + %1 = call i32 @llvm.dx.resource.updatecounter(target("dx.TypedBuffer", <4 x float>, 0, 0, 0) %buffer, i8 -1) ret void } @@ -20,11 +20,11 @@ define void @update_counter_decrement_vector() { define void @update_counter_increment_vector() { ; CHECK: [[BIND:%.*]] = call %dx.types.Handle @dx.op.createHandleFromBinding(i32 217, %buffer = call target("dx.TypedBuffer", <4 x float>, 0, 0, 0) - @llvm.dx.handle.fromBinding.tdx.TypedBuffer_v4f32_0_0_0( + @llvm.dx.resource.handlefrombinding.tdx.TypedBuffer_v4f32_0_0_0( i32 0, i32 0, i32 1, i32 0, i1 false) ; CHECK-NEXT: [[BUFFANOT:%.*]] = call %dx.types.Handle @dx.op.annotateHandle(i32 216, %dx.types.Handle [[BIND]] ; CHECK-NEXT: [[REG:%.*]] = call i32 @dx.op.bufferUpdateCounter(i32 70, %dx.types.Handle [[BUFFANOT]], i8 1) - %1 = call i32 @llvm.dx.bufferUpdateCounter(target("dx.TypedBuffer", <4 x float>, 0, 0, 0) %buffer, i8 1) + %1 = call i32 @llvm.dx.resource.updatecounter(target("dx.TypedBuffer", <4 x float>, 0, 0, 0) %buffer, i8 1) ret void } @@ -32,10 +32,10 @@ define void @update_counter_increment_vector() { define void @update_counter_decrement_scalar() { ; CHECK: [[BIND:%.*]] = call %dx.types.Handle @dx.op.createHandleFromBinding(i32 217, %buffer = call target("dx.RawBuffer", i8, 0, 0) - @llvm.dx.handle.fromBinding.tdx.RawBuffer_i8_0_0t( + @llvm.dx.resource.handlefrombinding.tdx.RawBuffer_i8_0_0t( i32 1, i32 8, i32 1, i32 0, i1 false) ; CHECK-NEXT: [[BUFFANOT:%.*]] = call %dx.types.Handle @dx.op.annotateHandle(i32 216, %dx.types.Handle [[BIND]] ; CHECK-NEXT: [[REG:%.*]] = call i32 @dx.op.bufferUpdateCounter(i32 70, %dx.types.Handle [[BUFFANOT]], i8 -1) - %1 = call i32 @llvm.dx.bufferUpdateCounter(target("dx.RawBuffer", i8, 0, 0) %buffer, i8 -1) + %1 = call i32 @llvm.dx.resource.updatecounter(target("dx.RawBuffer", i8, 0, 0) %buffer, i8 -1) ret void } diff --git a/llvm/test/CodeGen/SPIRV/hlsl-resources/BufferLoad.ll b/llvm/test/CodeGen/SPIRV/hlsl-resources/BufferLoad.ll index c2749d13c214d2..58252fe297f3e1 100644 --- a/llvm/test/CodeGen/SPIRV/hlsl-resources/BufferLoad.ll +++ b/llvm/test/CodeGen/SPIRV/hlsl-resources/BufferLoad.ll @@ -19,11 +19,11 @@ define void @RWBufferLoad_Vec4_I32() #0 { ; CHECK: [[buffer:%[0-9]+]] = OpLoad [[RWBufferTypeInt]] [[IntBufferVar]] %buffer0 = call target("spirv.Image", i32, 5, 2, 0, 0, 2, 24) - @llvm.spv.handle.fromBinding.tspirv.Image_i32_5_2_0_0_2_24( + @llvm.spv.resource.handlefrombinding.tspirv.Image_i32_5_2_0_0_2_24( i32 16, i32 7, i32 1, i32 0, i1 false) ; CHECK: OpImageRead [[v4_int]] [[buffer]] [[zero]] - %data0 = call <4 x i32> @llvm.spv.typedBufferLoad( + %data0 = call <4 x i32> @llvm.spv.resource.load.typedbuffer( target("spirv.Image", i32, 5, 2, 0, 0, 2, 24) %buffer0, i32 0) ret void @@ -34,12 +34,12 @@ define void @RWBufferLoad_Vec4_I32() #0 { define void @RWBufferLoad_I32() #0 { ; CHECK: [[buffer:%[0-9]+]] = OpLoad [[RWBufferTypeInt]] [[IntBufferVar]] %buffer1 = call target("spirv.Image", i32, 5, 2, 0, 0, 2, 24) - @llvm.spv.handle.fromBinding.tspirv.Image_i32_5_2_0_0_2_24( + @llvm.spv.resource.handlefrombinding.tspirv.Image_i32_5_2_0_0_2_24( i32 16, i32 7, i32 1, i32 0, i1 false) ; CHECK: [[V:%[0-9]+]] = OpImageRead [[v4_int]] [[buffer]] [[zero]] ; CHECK: OpCompositeExtract [[int]] [[V]] 0 - %data1 = call i32 @llvm.spv.typedBufferLoad( + %data1 = call i32 @llvm.spv.resource.load.typedbuffer( target("spirv.Image", i32, 5, 2, 0, 0, 2, 24) %buffer1, i32 0) ret void @@ -50,14 +50,14 @@ define void @RWBufferLoad_I32() #0 { define void @RWBufferLoad_Vec2_I32() #0 { ; CHECK: [[buffer:%[0-9]+]] = OpLoad [[RWBufferTypeInt]] [[IntBufferVar]] %buffer0 = call target("spirv.Image", i32, 5, 2, 0, 0, 2, 24) - @llvm.spv.handle.fromBinding.tspirv.Image_i32_5_2_0_0_2_24( + @llvm.spv.resource.handlefrombinding.tspirv.Image_i32_5_2_0_0_2_24( i32 16, i32 7, i32 1, i32 0, i1 false) ; CHECK: [[V:%[0-9]+]] = OpImageRead [[v4_int]] [[buffer]] [[zero]] ; CHECK: [[e0:%[0-9]+]] = OpCompositeExtract [[int]] [[V]] 0 ; CHECK: [[e1:%[0-9]+]] = OpCompositeExtract [[int]] [[V]] 1 ; CHECK: OpCompositeConstruct [[v2_int]] [[e0]] [[e1]] - %data0 = call <2 x i32> @llvm.spv.typedBufferLoad( + %data0 = call <2 x i32> @llvm.spv.resource.load.typedbuffer( target("spirv.Image", i32, 5, 2, 0, 0, 2, 24) %buffer0, i32 0) ret void diff --git a/llvm/test/CodeGen/SPIRV/hlsl-resources/BufferStore.ll b/llvm/test/CodeGen/SPIRV/hlsl-resources/BufferStore.ll index afcc0ed0a455d8..b0ffa01ccdd44d 100644 --- a/llvm/test/CodeGen/SPIRV/hlsl-resources/BufferStore.ll +++ b/llvm/test/CodeGen/SPIRV/hlsl-resources/BufferStore.ll @@ -22,13 +22,13 @@ declare <4 x i32> @get_data() #1 define void @RWBufferStore_Vec4_I32() #0 { ; CHECK: [[buffer:%[0-9]+]] = OpLoad [[RWBufferTypeInt]] [[IntBufferVar]] %buffer0 = call target("spirv.Image", i32, 5, 2, 0, 0, 2, 24) - @llvm.spv.handle.fromBinding.tspirv.Image_i32_5_2_0_0_2_24( + @llvm.spv.resource.handlefrombinding.tspirv.Image_i32_5_2_0_0_2_24( i32 16, i32 7, i32 1, i32 0, i1 false) ; CHECK: [[data:%[0-9]+]] = OpFunctionCall %data = call <4 x i32> @get_data() ; CHECK: OpImageWrite [[buffer]] [[zero]] [[data]] - call void @llvm.spv.typedBufferStore(target("spirv.Image", i32, 5, 2, 0, 0, 2, 24) %buffer0, i32 0, <4 x i32> %data) + call void @llvm.spv.resource.store.typedbuffer(target("spirv.Image", i32, 5, 2, 0, 0, 2, 24) %buffer0, i32 0, <4 x i32> %data) ret void } diff --git a/llvm/test/CodeGen/SPIRV/hlsl-resources/CombinedSamplerImageDynIdx.ll b/llvm/test/CodeGen/SPIRV/hlsl-resources/CombinedSamplerImageDynIdx.ll index 7a21a6c4bf7ea2..97a7252eb067b6 100644 --- a/llvm/test/CodeGen/SPIRV/hlsl-resources/CombinedSamplerImageDynIdx.ll +++ b/llvm/test/CodeGen/SPIRV/hlsl-resources/CombinedSamplerImageDynIdx.ll @@ -26,13 +26,13 @@ define void @main() #0 { ; CHECK: [[ac:%[0-9]+]] = OpAccessChain [[BufferPtrType]] [[Var]] [[Zero]] ; CHECK: [[buffer:%[0-9]+]] = OpLoad [[CombindedType]] [[ac]] %buffer0 = call target("spirv.SampledImage", i32, 0, 2, 0, 0, 1, 24) - @llvm.spv.handle.fromBinding.tspirv.Image_f32_0_2_0_0_1_24( + @llvm.spv.resource.handlefrombinding.tspirv.Image_f32_0_2_0_0_1_24( i32 3, i32 4, i32 3, i32 0, i1 false) ; CHECK: [[ac:%[0-9]+]] = OpAccessChain [[BufferPtrType]] [[Var]] [[One]] ; CHECK: [[buffer:%[0-9]+]] = OpLoad [[CombindedType]] [[ac]] %buffer1 = call target("spirv.SampledImage", i32, 0, 2, 0, 0, 1, 24) - @llvm.spv.handle.fromBinding.tspirv.Image_f32_0_2_0_0_1_24( + @llvm.spv.resource.handlefrombinding.tspirv.Image_f32_0_2_0_0_1_24( i32 3, i32 4, i32 3, i32 1, i1 false) ret void } diff --git a/llvm/test/CodeGen/SPIRV/hlsl-resources/CombinedSamplerImageNonUniformIdx.ll b/llvm/test/CodeGen/SPIRV/hlsl-resources/CombinedSamplerImageNonUniformIdx.ll index b821f5bdfa1370..6c5c126e4462b6 100644 --- a/llvm/test/CodeGen/SPIRV/hlsl-resources/CombinedSamplerImageNonUniformIdx.ll +++ b/llvm/test/CodeGen/SPIRV/hlsl-resources/CombinedSamplerImageNonUniformIdx.ll @@ -33,13 +33,13 @@ define void @main() #0 { ; CHECK: [[ac0]] = OpAccessChain [[BufferPtrType]] [[Var]] [[Zero]] ; CHECK: [[ld0:%[0-9]+]] = OpLoad [[CombindedType]] [[ac0]] %buffer0 = call target("spirv.SampledImage", i32, 0, 2, 0, 0, 1, 24) - @llvm.spv.handle.fromBinding.tspirv.Image_f32_0_2_0_0_1_24( + @llvm.spv.resource.handlefrombinding.tspirv.Image_f32_0_2_0_0_1_24( i32 3, i32 4, i32 3, i32 0, i1 true) ; CHECK: [[ac1]] = OpAccessChain [[BufferPtrType]] [[Var]] [[One]] ; CHECK: [[ld1]] = OpLoad [[CombindedType]] [[ac1]] %buffer1 = call target("spirv.SampledImage", i32, 0, 2, 0, 0, 1, 24) - @llvm.spv.handle.fromBinding.tspirv.Image_f32_0_2_0_0_1_24( + @llvm.spv.resource.handlefrombinding.tspirv.Image_f32_0_2_0_0_1_24( i32 3, i32 4, i32 3, i32 1, i1 true) ret void } diff --git a/llvm/test/CodeGen/SPIRV/hlsl-resources/InputAttachmentImageDynIdx.ll b/llvm/test/CodeGen/SPIRV/hlsl-resources/InputAttachmentImageDynIdx.ll index c925be1f8216ad..2a52dd1817f0cf 100644 --- a/llvm/test/CodeGen/SPIRV/hlsl-resources/InputAttachmentImageDynIdx.ll +++ b/llvm/test/CodeGen/SPIRV/hlsl-resources/InputAttachmentImageDynIdx.ll @@ -25,13 +25,13 @@ define void @main() #0 { ; CHECK: [[ac:%[0-9]+]] = OpAccessChain [[BufferPtrType]] [[Var]] [[Zero]] ; CHECK: [[buffer:%[0-9]+]] = OpLoad [[BufferType]] [[ac]] %buffer0 = call target("spirv.Image", i32, 6, 2, 0, 0, 2, 0) - @llvm.spv.handle.fromBinding.tspirv.Image_f32_6_2_0_0_2_0( + @llvm.spv.resource.handlefrombinding.tspirv.Image_f32_6_2_0_0_2_0( i32 3, i32 4, i32 3, i32 0, i1 false) ; CHECK: [[ac:%[0-9]+]] = OpAccessChain [[BufferPtrType]] [[Var]] [[One]] ; CHECK: [[buffer:%[0-9]+]] = OpLoad [[BufferType]] [[ac]] %buffer1 = call target("spirv.Image", i32, 6, 2, 0, 0, 2, 0) - @llvm.spv.handle.fromBinding.tspirv.Image_f32_6_2_0_0_2_0( + @llvm.spv.resource.handlefrombinding.tspirv.Image_f32_6_2_0_0_2_0( i32 3, i32 4, i32 3, i32 1, i1 false) ret void } diff --git a/llvm/test/CodeGen/SPIRV/hlsl-resources/InputAttachmentImageNonUniformIdx.ll b/llvm/test/CodeGen/SPIRV/hlsl-resources/InputAttachmentImageNonUniformIdx.ll index bb2e7549fd3ba8..6dae79c5b385d3 100644 --- a/llvm/test/CodeGen/SPIRV/hlsl-resources/InputAttachmentImageNonUniformIdx.ll +++ b/llvm/test/CodeGen/SPIRV/hlsl-resources/InputAttachmentImageNonUniformIdx.ll @@ -32,13 +32,13 @@ define void @main() #0 { ; CHECK: [[ac0]] = OpAccessChain [[BufferPtrType]] [[Var]] [[Zero]] ; CHECK: [[ld0]] = OpLoad [[BufferType]] [[ac0]] %buffer0 = call target("spirv.Image", i32, 6, 2, 0, 0, 2, 0) - @llvm.spv.handle.fromBinding.tspirv.Image_f32_6_2_0_0_2_0( + @llvm.spv.resource.handlefrombinding.tspirv.Image_f32_6_2_0_0_2_0( i32 3, i32 4, i32 3, i32 0, i1 true) ; CHECK: [[ac1:%[0-9]+]] = OpAccessChain [[BufferPtrType]] [[Var]] [[One]] ; CHECK: [[ld1]] = OpLoad [[BufferType]] [[ac1]] %buffer1 = call target("spirv.Image", i32, 6, 2, 0, 0, 2, 0) - @llvm.spv.handle.fromBinding.tspirv.Image_f32_6_2_0_0_2_0( + @llvm.spv.resource.handlefrombinding.tspirv.Image_f32_6_2_0_0_2_0( i32 3, i32 4, i32 3, i32 1, i1 true) ret void } diff --git a/llvm/test/CodeGen/SPIRV/hlsl-resources/SampledImageDynIdx.ll b/llvm/test/CodeGen/SPIRV/hlsl-resources/SampledImageDynIdx.ll index 69b1ac9078ff65..efd89c5977f970 100644 --- a/llvm/test/CodeGen/SPIRV/hlsl-resources/SampledImageDynIdx.ll +++ b/llvm/test/CodeGen/SPIRV/hlsl-resources/SampledImageDynIdx.ll @@ -32,13 +32,13 @@ define void @main() #0 { ; CHECK: [[ac:%[0-9]+]] = OpAccessChain [[BufferPtrType]] [[Var]] [[Zero]] ; CHECK: [[buffer:%[0-9]+]] = OpLoad [[BufferType]] [[ac]] %buffer0 = call target("spirv.Image", i32, 0, 2, 0, 0, 1, 24) - @llvm.spv.handle.fromBinding.tspirv.Image_f32_0_2_0_0_1_24( + @llvm.spv.resource.handlefrombinding.tspirv.Image_f32_0_2_0_0_1_24( i32 3, i32 4, i32 3, i32 0, i1 false) ; CHECK: [[ac:%[0-9]+]] = OpAccessChain [[BufferPtrType]] [[Var]] [[One]] ; CHECK: [[buffer:%[0-9]+]] = OpLoad [[BufferType]] [[ac]] %buffer1 = call target("spirv.Image", i32, 0, 2, 0, 0, 1, 24) - @llvm.spv.handle.fromBinding.tspirv.Image_f32_0_2_0_0_1_24( + @llvm.spv.resource.handlefrombinding.tspirv.Image_f32_0_2_0_0_1_24( i32 3, i32 4, i32 3, i32 1, i1 false) ret void } @@ -51,13 +51,13 @@ define void @DifferentArraySizesAreDifferentVariables() #0 { ; CHECK: [[ac:%[0-9]+]] = OpAccessChain [[BufferPtrType]] [[Var]] [[Zero]] ; CHECK: [[buffer:%[0-9]+]] = OpLoad [[BufferType]] [[ac]] %buffer0 = call target("spirv.Image", i32, 0, 2, 0, 0, 1, 24) - @llvm.spv.handle.fromBinding.tspirv.Image_f32_0_2_0_0_1_24( + @llvm.spv.resource.handlefrombinding.tspirv.Image_f32_0_2_0_0_1_24( i32 3, i32 4, i32 3, i32 0, i1 false) ; CHECK: [[ac:%[0-9]+]] = OpAccessChain [[BufferPtrType]] [[OtherVar]] [[One]] ; CHECK: [[buffer:%[0-9]+]] = OpLoad [[BufferType]] [[ac]] %buffer1 = call target("spirv.Image", i32, 0, 2, 0, 0, 1, 24) - @llvm.spv.handle.fromBinding.tspirv.Image_f32_0_2_0_0_1_24( + @llvm.spv.resource.handlefrombinding.tspirv.Image_f32_0_2_0_0_1_24( i32 3, i32 4, i32 5, i32 1, i1 false) ret void } diff --git a/llvm/test/CodeGen/SPIRV/hlsl-resources/SampledImageNonUniformIdx.ll b/llvm/test/CodeGen/SPIRV/hlsl-resources/SampledImageNonUniformIdx.ll index 7d1865aca67350..6d93051ce3f0a0 100644 --- a/llvm/test/CodeGen/SPIRV/hlsl-resources/SampledImageNonUniformIdx.ll +++ b/llvm/test/CodeGen/SPIRV/hlsl-resources/SampledImageNonUniformIdx.ll @@ -32,13 +32,13 @@ define void @main() #0 { ; CHECK: [[ac0]] = OpAccessChain [[BufferPtrType]] [[Var]] [[Zero]] ; CHECK: [[ld0]] = OpLoad [[BufferType]] [[ac0]] %buffer0 = call target("spirv.Image", i32, 0, 2, 0, 0, 1, 24) - @llvm.spv.handle.fromBinding.tspirv.Image_f32_0_2_0_0_1_24( + @llvm.spv.resource.handlefrombinding.tspirv.Image_f32_0_2_0_0_1_24( i32 3, i32 4, i32 3, i32 0, i1 true) ; CHECK: [[ac1:%[0-9]+]] = OpAccessChain [[BufferPtrType]] [[Var]] [[One]] ; CHECK: [[ld1]] = OpLoad [[BufferType]] [[ac1]] %buffer1 = call target("spirv.Image", i32, 0, 2, 0, 0, 1, 24) - @llvm.spv.handle.fromBinding.tspirv.Image_f32_0_2_0_0_1_24( + @llvm.spv.resource.handlefrombinding.tspirv.Image_f32_0_2_0_0_1_24( i32 3, i32 4, i32 3, i32 1, i1 true) ret void } diff --git a/llvm/test/CodeGen/SPIRV/hlsl-resources/SamplerArrayDynIdx.ll b/llvm/test/CodeGen/SPIRV/hlsl-resources/SamplerArrayDynIdx.ll index 3ca6788f0e48a7..fd276e9ef4a986 100644 --- a/llvm/test/CodeGen/SPIRV/hlsl-resources/SamplerArrayDynIdx.ll +++ b/llvm/test/CodeGen/SPIRV/hlsl-resources/SamplerArrayDynIdx.ll @@ -24,13 +24,13 @@ define void @main() #0 { ; CHECK: [[ac:%[0-9]+]] = OpAccessChain [[SamplerPtrType]] [[Var]] [[Zero]] ; CHECK: [[buffer:%[0-9]+]] = OpLoad [[SamplerType]] [[ac]] %buffer0 = call target("spirv.Sampler") - @llvm.spv.handle.fromBinding.tspirv.Image( + @llvm.spv.resource.handlefrombinding.tspirv.Image( i32 3, i32 4, i32 3, i32 0, i1 false) ; CHECK: [[ac:%[0-9]+]] = OpAccessChain [[SamplerPtrType]] [[Var]] [[One]] ; CHECK: [[buffer:%[0-9]+]] = OpLoad [[SamplerType]] [[ac]] %buffer1 = call target("spirv.Sampler") - @llvm.spv.handle.fromBinding.tspirv.Image( + @llvm.spv.resource.handlefrombinding.tspirv.Image( i32 3, i32 4, i32 3, i32 1, i1 false) ret void } diff --git a/llvm/test/CodeGen/SPIRV/hlsl-resources/SamplerArrayNonUniformIdx.ll b/llvm/test/CodeGen/SPIRV/hlsl-resources/SamplerArrayNonUniformIdx.ll index 0917d4751f459f..3e59d66febf0b5 100644 --- a/llvm/test/CodeGen/SPIRV/hlsl-resources/SamplerArrayNonUniformIdx.ll +++ b/llvm/test/CodeGen/SPIRV/hlsl-resources/SamplerArrayNonUniformIdx.ll @@ -31,13 +31,13 @@ define void @main() #0 { ; CHECK: [[ac0]] = OpAccessChain [[SamplerPtrType]] [[Var]] [[Zero]] ; CHECK: [[ld0]] = OpLoad [[SamplerType]] [[ac0]] %buffer0 = call target("spirv.Sampler") - @llvm.spv.handle.fromBinding.tspirv.Image( + @llvm.spv.resource.handlefrombinding.tspirv.Image( i32 3, i32 4, i32 3, i32 0, i1 true) ; CHECK: [[ac1:%[0-9]+]] = OpAccessChain [[SamplerPtrType]] [[Var]] [[One]] ; CHECK: [[ld1]] = OpLoad [[SamplerType]] [[ac1]] %buffer1 = call target("spirv.Sampler") - @llvm.spv.handle.fromBinding.tspirv.Image( + @llvm.spv.resource.handlefrombinding.tspirv.Image( i32 3, i32 4, i32 3, i32 1, i1 true) ret void } diff --git a/llvm/test/CodeGen/SPIRV/hlsl-resources/ScalarResourceType.ll b/llvm/test/CodeGen/SPIRV/hlsl-resources/ScalarResourceType.ll index b264227771c335..52cc2275bc7a6e 100644 --- a/llvm/test/CodeGen/SPIRV/hlsl-resources/ScalarResourceType.ll +++ b/llvm/test/CodeGen/SPIRV/hlsl-resources/ScalarResourceType.ll @@ -20,13 +20,13 @@ define void @RWBufferLoad() #0 { ; CHECK: [[buffer:%[0-9]+]] = OpLoad [[RWBufferTypeInt]] [[IntBufferVar]] %buffer0 = call target("spirv.Image", i32, 5, 2, 0, 0, 2, 24) - @llvm.spv.handle.fromBinding.tspirv.Image_f32_5_2_0_0_2_24( + @llvm.spv.resource.handlefrombinding.tspirv.Image_f32_5_2_0_0_2_24( i32 16, i32 7, i32 1, i32 0, i1 false) ; Make sure we use the same variable with multiple loads. ; CHECK: [[buffer:%[0-9]+]] = OpLoad [[RWBufferTypeInt]] [[IntBufferVar]] %buffer1 = call target("spirv.Image", i32, 5, 2, 0, 0, 2, 24) - @llvm.spv.handle.fromBinding.tspirv.Image_f32_5_2_0_0_2_24( + @llvm.spv.resource.handlefrombinding.tspirv.Image_f32_5_2_0_0_2_24( i32 16, i32 7, i32 1, i32 0, i1 false) ret void } @@ -38,7 +38,7 @@ define void @UseDifferentGlobalVar() #0 { ; different types. ; CHECK: [[buffer:%[0-9]+]] = OpLoad [[RWBufferTypeFloat]] [[FloatBufferVar]] %buffer0 = call target("spirv.Image", float, 5, 2, 0, 0, 2, 3) - @llvm.spv.handle.fromBinding.tspirv.Image_f32_5_2_0_0_2_3( + @llvm.spv.resource.handlefrombinding.tspirv.Image_f32_5_2_0_0_2_3( i32 16, i32 7, i32 1, i32 0, i1 false) ret void } @@ -50,7 +50,7 @@ define void @ReuseGlobalVarFromFirstFunction() #0 { ; same in case one function calls the other. ; CHECK: [[buffer:%[0-9]+]] = OpLoad [[RWBufferTypeInt]] [[IntBufferVar]] %buffer1 = call target("spirv.Image", i32, 5, 2, 0, 0, 2, 24) - @llvm.spv.handle.fromBinding.tspirv.Image_f32_5_2_0_0_2_24( + @llvm.spv.resource.handlefrombinding.tspirv.Image_f32_5_2_0_0_2_24( i32 16, i32 7, i32 1, i32 0, i1 false) ret void } diff --git a/llvm/test/CodeGen/SPIRV/hlsl-resources/StorageImageDynIdx.ll b/llvm/test/CodeGen/SPIRV/hlsl-resources/StorageImageDynIdx.ll index 1922e663883246..082a5c832f1c4c 100644 --- a/llvm/test/CodeGen/SPIRV/hlsl-resources/StorageImageDynIdx.ll +++ b/llvm/test/CodeGen/SPIRV/hlsl-resources/StorageImageDynIdx.ll @@ -25,13 +25,13 @@ define void @main() #0 { ; CHECK: [[ac:%[0-9]+]] = OpAccessChain [[BufferPtrType]] [[Var]] [[Zero]] ; CHECK: [[buffer:%[0-9]+]] = OpLoad [[BufferType]] [[ac]] %buffer0 = call target("spirv.Image", i32, 0, 2, 0, 0, 2, 24) - @llvm.spv.handle.fromBinding.tspirv.Image_f32_0_2_0_0_2_24( + @llvm.spv.resource.handlefrombinding.tspirv.Image_f32_0_2_0_0_2_24( i32 3, i32 4, i32 3, i32 0, i1 false) ; CHECK: [[ac:%[0-9]+]] = OpAccessChain [[BufferPtrType]] [[Var]] [[One]] ; CHECK: [[buffer:%[0-9]+]] = OpLoad [[BufferType]] [[ac]] %buffer1 = call target("spirv.Image", i32, 0, 2, 0, 0, 2, 24) - @llvm.spv.handle.fromBinding.tspirv.Image_f32_0_2_0_0_2_24( + @llvm.spv.resource.handlefrombinding.tspirv.Image_f32_0_2_0_0_2_24( i32 3, i32 4, i32 3, i32 1, i1 false) ret void } diff --git a/llvm/test/CodeGen/SPIRV/hlsl-resources/StorageImageNonUniformIdx.ll b/llvm/test/CodeGen/SPIRV/hlsl-resources/StorageImageNonUniformIdx.ll index 231e1cf7567a0b..d6419492bb9529 100644 --- a/llvm/test/CodeGen/SPIRV/hlsl-resources/StorageImageNonUniformIdx.ll +++ b/llvm/test/CodeGen/SPIRV/hlsl-resources/StorageImageNonUniformIdx.ll @@ -32,13 +32,13 @@ define void @main() #0 { ; CHECK: [[ac0]] = OpAccessChain [[BufferPtrType]] [[Var]] [[Zero]] ; CHECK: [[ld0]] = OpLoad [[BufferType]] [[ac0]] %buffer0 = call target("spirv.Image", i32, 0, 2, 0, 0, 2, 24) - @llvm.spv.handle.fromBinding.tspirv.Image_f32_0_2_0_0_2_24( + @llvm.spv.resource.handlefrombinding.tspirv.Image_f32_0_2_0_0_2_24( i32 3, i32 4, i32 3, i32 0, i1 true) ; CHECK: [[ac1:%[0-9]+]] = OpAccessChain [[BufferPtrType]] [[Var]] [[One]] ; CHECK: [[ld1]] = OpLoad [[BufferType]] [[ac1]] %buffer1 = call target("spirv.Image", i32, 0, 2, 0, 0, 2, 24) - @llvm.spv.handle.fromBinding.tspirv.Image_f32_0_2_0_0_2_24( + @llvm.spv.resource.handlefrombinding.tspirv.Image_f32_0_2_0_0_2_24( i32 3, i32 4, i32 3, i32 1, i1 true) ret void } diff --git a/llvm/test/CodeGen/SPIRV/hlsl-resources/StorageTexelBufferDynIdx.ll b/llvm/test/CodeGen/SPIRV/hlsl-resources/StorageTexelBufferDynIdx.ll index 454ba1f47db0a7..31fdcb362eb739 100644 --- a/llvm/test/CodeGen/SPIRV/hlsl-resources/StorageTexelBufferDynIdx.ll +++ b/llvm/test/CodeGen/SPIRV/hlsl-resources/StorageTexelBufferDynIdx.ll @@ -25,13 +25,13 @@ define void @void() #0 { ; CHECK: [[ac:%[0-9]+]] = OpAccessChain [[BufferPtrType]] [[Var]] [[Zero]] ; CHECK: [[buffer:%[0-9]+]] = OpLoad [[BufferType]] [[ac]] %buffer0 = call target("spirv.Image", i32, 5, 2, 0, 0, 2, 24) - @llvm.spv.handle.fromBinding.tspirv.Image_f32_5_2_0_0_2_24( + @llvm.spv.resource.handlefrombinding.tspirv.Image_f32_5_2_0_0_2_24( i32 3, i32 4, i32 3, i32 0, i1 false) ; CHECK: [[ac:%[0-9]+]] = OpAccessChain [[BufferPtrType]] [[Var]] [[One]] ; CHECK: [[buffer:%[0-9]+]] = OpLoad [[BufferType]] [[ac]] %buffer1 = call target("spirv.Image", i32, 5, 2, 0, 0, 2, 24) - @llvm.spv.handle.fromBinding.tspirv.Image_f32_5_2_0_0_2_24( + @llvm.spv.resource.handlefrombinding.tspirv.Image_f32_5_2_0_0_2_24( i32 3, i32 4, i32 3, i32 1, i1 false) ret void } diff --git a/llvm/test/CodeGen/SPIRV/hlsl-resources/StorageTexelBufferNonUniformIdx.ll b/llvm/test/CodeGen/SPIRV/hlsl-resources/StorageTexelBufferNonUniformIdx.ll index a579aaa1eed696..a5608979025fe1 100644 --- a/llvm/test/CodeGen/SPIRV/hlsl-resources/StorageTexelBufferNonUniformIdx.ll +++ b/llvm/test/CodeGen/SPIRV/hlsl-resources/StorageTexelBufferNonUniformIdx.ll @@ -32,13 +32,13 @@ define void @main() #0 { ; CHECK: [[ac0]] = OpAccessChain [[BufferPtrType]] [[Var]] [[Zero]] ; CHECK: [[ld0]] = OpLoad [[BufferType]] [[ac0]] %buffer0 = call target("spirv.Image", i32, 5, 2, 0, 0, 2, 24) - @llvm.spv.handle.fromBinding.tspirv.Image_f32_5_2_0_0_2_24( + @llvm.spv.resource.handlefrombinding.tspirv.Image_f32_5_2_0_0_2_24( i32 3, i32 4, i32 3, i32 0, i1 true) ; CHECK: [[ac1:%[0-9]+]] = OpAccessChain [[BufferPtrType]] [[Var]] [[One]] ; CHECK: [[ld1]] = OpLoad [[BufferType]] [[ac1]] %buffer1 = call target("spirv.Image", i32, 5, 2, 0, 0, 2, 24) - @llvm.spv.handle.fromBinding.tspirv.Image_f32_5_2_0_0_2_24( + @llvm.spv.resource.handlefrombinding.tspirv.Image_f32_5_2_0_0_2_24( i32 3, i32 4, i32 3, i32 1, i1 true) ret void } diff --git a/llvm/test/CodeGen/SPIRV/hlsl-resources/UniformTexelBufferDynIdx.ll b/llvm/test/CodeGen/SPIRV/hlsl-resources/UniformTexelBufferDynIdx.ll index 98c4ff7a965d58..131a6b38d393e1 100644 --- a/llvm/test/CodeGen/SPIRV/hlsl-resources/UniformTexelBufferDynIdx.ll +++ b/llvm/test/CodeGen/SPIRV/hlsl-resources/UniformTexelBufferDynIdx.ll @@ -25,13 +25,13 @@ define void @main() #0 { ; CHECK: [[ac:%[0-9]+]] = OpAccessChain [[BufferPtrType]] [[Var]] [[Zero]] ; CHECK: [[buffer:%[0-9]+]] = OpLoad [[BufferType]] [[ac]] %buffer0 = call target("spirv.Image", i32, 5, 2, 0, 0, 1, 24) - @llvm.spv.handle.fromBinding.tspirv.Image_f32_5_2_0_0_1_24( + @llvm.spv.resource.handlefrombinding.tspirv.Image_f32_5_2_0_0_1_24( i32 3, i32 4, i32 3, i32 0, i1 false) ; CHECK: [[ac:%[0-9]+]] = OpAccessChain [[BufferPtrType]] [[Var]] [[One]] ; CHECK: [[buffer:%[0-9]+]] = OpLoad [[BufferType]] [[ac]] %buffer1 = call target("spirv.Image", i32, 5, 2, 0, 0, 1, 24) - @llvm.spv.handle.fromBinding.tspirv.Image_f32_5_2_0_0_1_24( + @llvm.spv.resource.handlefrombinding.tspirv.Image_f32_5_2_0_0_1_24( i32 3, i32 4, i32 3, i32 1, i1 false) ret void } diff --git a/llvm/test/CodeGen/SPIRV/hlsl-resources/UniformTexelBufferNonUniformIdx.ll b/llvm/test/CodeGen/SPIRV/hlsl-resources/UniformTexelBufferNonUniformIdx.ll index da523f215046b7..cfb3eb5f520764 100644 --- a/llvm/test/CodeGen/SPIRV/hlsl-resources/UniformTexelBufferNonUniformIdx.ll +++ b/llvm/test/CodeGen/SPIRV/hlsl-resources/UniformTexelBufferNonUniformIdx.ll @@ -32,13 +32,13 @@ define void @main() #0 { ; CHECK: [[ac0]] = OpAccessChain [[BufferPtrType]] [[Var]] [[Zero]] ; CHECK: [[ld0]] = OpLoad [[BufferType]] [[ac0]] %buffer0 = call target("spirv.Image", i32, 5, 2, 0, 0, 1, 24) - @llvm.spv.handle.fromBinding.tspirv.Image_f32_5_2_0_0_1_24( + @llvm.spv.resource.handlefrombinding.tspirv.Image_f32_5_2_0_0_1_24( i32 3, i32 4, i32 3, i32 0, i1 true) ; CHECK: [[ac1:%[0-9]+]] = OpAccessChain [[BufferPtrType]] [[Var]] [[One]] ; CHECK: [[ld1]] = OpLoad [[BufferType]] [[ac1]] %buffer1 = call target("spirv.Image", i32, 5, 2, 0, 0, 1, 24) - @llvm.spv.handle.fromBinding.tspirv.Image_f32_5_2_0_0_1_24( + @llvm.spv.resource.handlefrombinding.tspirv.Image_f32_5_2_0_0_1_24( i32 3, i32 4, i32 3, i32 1, i1 true) ret void } diff --git a/llvm/test/CodeGen/SPIRV/hlsl-resources/UnknownBufferLoad.ll b/llvm/test/CodeGen/SPIRV/hlsl-resources/UnknownBufferLoad.ll index 7f9c6f7da2859e..4ec8605f68137d 100644 --- a/llvm/test/CodeGen/SPIRV/hlsl-resources/UnknownBufferLoad.ll +++ b/llvm/test/CodeGen/SPIRV/hlsl-resources/UnknownBufferLoad.ll @@ -17,11 +17,11 @@ define void @RWBufferLoad_Vec4_I32() #0 { ; CHECK: [[buffer:%[0-9]+]] = OpLoad [[RWBufferTypeInt]] [[IntBufferVar]] %buffer0 = call target("spirv.Image", i32, 5, 2, 0, 0, 2, 0) - @llvm.spv.handle.fromBinding.tspirv.Image_f32_5_2_0_0_2_0( + @llvm.spv.resource.handlefrombinding.tspirv.Image_f32_5_2_0_0_2_0( i32 16, i32 7, i32 1, i32 0, i1 false) ; CHECK: OpImageRead [[v4_int]] [[buffer]] [[zero]] - %data0 = call <4 x i32> @llvm.spv.typedBufferLoad( + %data0 = call <4 x i32> @llvm.spv.resource.load.typedbuffer( target("spirv.Image", i32, 5, 2, 0, 0, 2, 0) %buffer0, i32 0) ret void diff --git a/llvm/test/CodeGen/SPIRV/hlsl-resources/UnknownBufferStore.ll b/llvm/test/CodeGen/SPIRV/hlsl-resources/UnknownBufferStore.ll index 4d26f502568149..4c6f9bfd97ed7b 100644 --- a/llvm/test/CodeGen/SPIRV/hlsl-resources/UnknownBufferStore.ll +++ b/llvm/test/CodeGen/SPIRV/hlsl-resources/UnknownBufferStore.ll @@ -20,13 +20,13 @@ declare <4 x i32> @get_data() #1 define void @RWBufferLoad_Vec4_I32() #0 { ; CHECK: [[buffer:%[0-9]+]] = OpLoad [[RWBufferTypeInt]] [[IntBufferVar]] %buffer0 = call target("spirv.Image", i32, 5, 2, 0, 0, 2, 0) - @llvm.spv.handle.fromBinding.tspirv.Image_f32_5_2_0_0_2_0( + @llvm.spv.resource.handlefrombinding.tspirv.Image_f32_5_2_0_0_2_0( i32 16, i32 7, i32 1, i32 0, i1 false) ; CHECK: [[data:%[0-9]+]] = OpFunctionCall %data = call <4 x i32> @get_data() ; CHECK: OpImageWrite [[buffer]] [[ten]] [[data]] - call void @llvm.spv.typedBufferStore( + call void @llvm.spv.resource.store.typedbuffer( target("spirv.Image", i32, 5, 2, 0, 0, 2, 0) %buffer0, i32 10, <4 x i32> %data) ret void