firtool-1.85.0

What's Changed

• [Seq] Introduce seq.initial, !seq.immutable and replace powerOn value with initial value in compreg by @uenoku in #7553
• [ESI] Add optional non-blocking write API to WriteChannelPort by @mortbopet in #7555
• [ESI][Runtime] Pretty printing of service ports by @teqdruid in #7567
• Bump LLVM to 10407be542aeb2b59477b167bbba3716538dc722. by @mikeurbach in #7550
• [ESI][Runtime] Address MMIO regions symbolically by @teqdruid in #7568
• [ESI] Don't assume using namespace std in Manifest.cpp by @mortbopet in #7571
• [FIRRTLUtils] Fix walkDrivers subfield id calculation by @uenoku in #7536
• [SV] Fix regop canonicalizer crashing. by @dtzSiFive in #7564
• [MooreToCore] Separate conversion pattern for moore.output by @maerhart in #7573
• [FIRRTL][GrandCentral] Fix crashes on error re:tryGetAs. by @dtzSiFive in #7576
• [FIRRTL][GrandCentral] Don't crash on missing keys, getAs. by @dtzSiFive in #7577
• [ESI] Manifest: change the schema to be more rational by @teqdruid in #7561
• [ESI][Runtime] Logging API by @teqdruid in #7569
• [MooreToCore] Support to lower unpacked struct type by @cepheus69 in #7565
• [Moore][NFC] Fix warning when building Moore components by @cepheus69 in #7566
• [ImportVerilog] Skip defparams which have been handled by slang. by @hailongSun2000 in #7582
• [HW] Fix crash when error encountered parsing hw.array. by @dtzSiFive in #7578
• [HW][HWTypes] Fix use of OptionalParseResult. by @dtzSiFive in #7575
• [FIRRTL][Folds] Fix mux fold if result type doesn't match operands. by @dtzSiFive in #7585
• [FIRRTL][Lexer] Don't crash on trailing slash in inline anno. by @dtzSiFive in #7579
• [FIRRTL][FIRParser] Defer inner symbols to post-processing, fix race. by @dtzSiFive in #7584
• [FIRRTL] Add back unambiguous path requirement. by @mikeurbach in #7588

Full Changelog: firtool-1.84.0...firtool-1.85.0

firtool-1.84.0

What's Changed

• [FIRRTL] Improve Layer Merge Performance by @seldridge in #7552
• [ESI] Make AcceleratorConnection::disconnect virtual by @mortbopet in #7554
• [FreezePaths] Add an optional argument, to get the operation name by @prithayan in #7549
• [ExportVerilog] Drop external module emission by @seldridge in #7558
• [firrtl] Add CheckLayers diagnostics pass by @youngar in #7547

Full Changelog: firtool-1.83.0...firtool-1.84.0

firtool-1.83.0

What's Changed

• [LLHD] Align signals with other wire/variable ops by @fabianschuiki in #7523
• [Moore] Improve WaitEventOp, lower to LLHD by @fabianschuiki in #7518
• [firrtl] Fix bug in sibling layer specialization by @seldridge in #7526
• [ExportVerilog] Avoid inlining unpacked array expressions to declarations for tool compatibility by @uenoku in #4548
• [LLHD] Let WaitOp observe plain values instead of signals by @maerhart in #7528
• [FIRRTL][FIRParser] Cache property constants. by @dtzSiFive in #7530
• [MooreToCore] Add always_comb and always_latch lowering support by @maerhart in #7532
• [ESI][Runtime] Generate C++ header files for constants by @teqdruid in #7517
• [CombFolds] Don't canonicalize extract(shl(1, x)) if shift is multiply used by @uenoku in #7527
• [MooreToCore] Ignore ConstantLike values in wait op by @fabianschuiki in #7540
• [FIRRTL][LowerLayers] Update rwprobe operations if possible. by @dtzSiFive in #7369
• [FIRRTL] Set output dirs on annotated blackboxes by @seldridge in #7541

Full Changelog: firtool-1.82.0...firtool-1.83.0

firtool-1.82.0

What's Changed

• [FIRRTL] Add list concatenation operation. by @mikeurbach in #7486
• [Verif] Generalize Formal Contracts by @dobios in #7495
• [FIRRTL] Add list concatenation parser support. by @mikeurbach in #7512
• [FIRRTL] Add list concatenation conversion to LowerClasses. by @mikeurbach in #7513
• Explain IR acronym in README by @parker-research in #7506
• [HW][CAPI] Add a function to get an empty InnerSymAttr by @SpriteOvO in #7504
• [PyCDE] Support for adding module constants to manifests by @teqdruid in #7510
• [Comb][Fold] Fix idemp n^2 and bugfix + more optimization. by @dtzSiFive in #7514
• [OM] Support list concatenation in the Evaluator. by @mikeurbach in #7511
• [LLHD] Relax sig parent constraint by @maerhart in #7515
• [Arc] Add Initial Cost Model by @elhewaty in #7360
• LowerLayers: fix how we emit layer bindfile headers by @rwy7 in #7516
• [FIRRTL] Add Inline Formal Test ops by @dobios in #7374
• [Arc] Add InitialOp and lowering support for FirReg preset values. by @fzi-hielscher in #7480
• [LowerIntmodules] Fix EICG_wrapper intrinsic lowering, swap en/test_en. by @dtzSiFive in #7519
• [firtool] Change layer specialization CLI interface by @youngar in #7520
• [FIRRTL] Add CheckRecursiveInstantiation diagnostic pass by @youngar in #7433
• [NFC] Add circt copy of upstream's linkify. by @dtzSiFive in #7521
• [FIRRTL] Update LowerClasses to alter what PathInfo stores. by @mikeurbach in #7522

New Contributors

• @parker-research made their first contribution in #7506

Full Changelog: firtool-1.81.1...firtool-1.82.0

firtool-1.81.1

What's Changed

• [Moore] Fix mem2reg implementation by @fabianschuiki in #7498
• [MooreToCore] More extract op lowerings by @maerhart in #7499
• [calyx] fix calyx canonicalization. by @linuxlonelyeagle in #7456
• [MooreToCore] Support AssignedVariableOp by @maerhart in #7500
• [MooreToCore] Support four-valued VariableOp without init by @fabianschuiki in #7502
• [MooreToCore] Support ConditionalOp by @fabianschuiki in #7501
• [MooreToCore] Support CaseZEq and CaseXZEq ops by @fabianschuiki in #7503
• [LLHD] Add llhd.delay operation by @maerhart in #7505
• [LLHD][NFC] Clean up regression tests a bit by @maerhart in #7507
• [LLHD] Remove RegOp by @maerhart in #7508
• [LLHD][NFC] Clean up some LLHD files by @maerhart in #7509
• [ESI][Manifest] Embed constants in manifest by @teqdruid in #7489
• [CreateSifiveMetadata] Update memory hierarchy paths to be pre-extrction by @prithayan in #7491
• [ESI][Runtime] Parse and expose manifest constants by @teqdruid in #7492
• [OM] Add list concatenation operation. by @mikeurbach in #7487

Full Changelog: firtool-1.81.0...firtool-1.81.1

firtool-1.81.0

What's Changed

• [ImportVerilog] Switch from SCF to CF dialect for control flow by @fabianschuiki in #7432
• [Docs][FIRRTL] Build and include docs for intrinsic ops by @SpriteOvO in #7444
• [CMake] Fix install failure with CMAKE_SLANG_FRONTEND_ENABLED enabled by @cepheus69 in #7437
• [Support] Allow erasing names in Namespace by @mortbopet in #7424
• [FIRRTL] Verify main module is a module, and is public. by @dtzSiFive in #7439
• [Ibis] Don't include design name in namespace in IbisContainersToHW by @mortbopet in #7425
• [FIRRTL] Verify RWProbeOp target has layer requirements. by @dtzSiFive in #7372
• [FIRRTL] Tweak printing of layers to avoid extra space. by @dtzSiFive in #7449
• Replaced 'replicate' to correctly named 'replace' flags by @jpien13 in #7442
• [Arc][Sim] Lower Sim DPI func to func.func and support dpi call in Arc by @uenoku in #7386
• [arcilator] Add an option to load shared lib into JIT engine by @uenoku in #7453
• [arcilator] Add JIT runtime environment library and stdio hooks by @fzi-hielscher in #7445
• [circt-lec] Accept two MLIR inputs by @uenoku in #7450
• [FIRRTL] Cache symbol table in LowerLayers by @seldridge in #7436
• [ExportVerilog] Add a lowering option to fix up empty modules by @uenoku in #7454
• [SimToSV] Add include guards to DPI import by @uenoku in #7459
• [ESI] Add option to build runtime as a static library by @mortbopet in #7455
• [ESI][Runtime] Poll method and optional service thread polling by @teqdruid in #7460
• [Moore] Add FVIntegerAttr by @fabianschuiki in #7461
• [Moore] Support four-valued integers in ConstantOp by @fabianschuiki in #7463
• [FIRRTL][Dedup] Reduce size of integer data hashed. by @dtzSiFive in #7469
• [FIRRTL][LowerLayers] Plumb support for errors. by @dtzSiFive in #7470
• [MooreToCore] Fix conversion and dyn_extract operation lowering by @maerhart in #7473
• [MooreToCore] Struct extract lowering support by @maerhart in #7475
• [FIRRTL][InferResets] Generalize FART to support sync reset by @jackkoenig in #7476
• [MooreToCore] Fix variable op lowering of aggregate types by @maerhart in #7481
• [MooreToCore] Support ProcedureOp and sequential assign operations by @maerhart in #7362
• [FIRRTL] Canonicalize multibit_mux with narrow index by @uenoku in #7373
• [FIRRTL] Fix sub-* op in layer block verifier by @seldridge in #7462
• [OM] Add AnyType C API and Python bindings. by @mikeurbach in #7488
• [OM] Add ListType C API and Python bindings. by @mikeurbach in #7490
• [HWArith] Make hwarith.icmp result an i1 by @teqdruid in #7413
• [Moore] Add more AssignedVariableOp canonicalizations by @fabianschuiki in #7477
• [Moore] Add constant materialization, fold constant conversions by @fabianschuiki in #7478
• bump llvm to tip of main by @mwachs5 in #7440
• [Moore] Power operator folders and canonicalizers by @maerhart in #7494
• [MooreToCore] Support StructExtractRefOp by @maerhart in #7497
• LLVM bump to include upstream verifier performance fix. by @dtzSiFive in #7496

New Contributors

• @jpien13 made their first contribution in #7442

Full Changelog: firtool-1.80.1...firtool-1.81.0

firtool-1.80.1

What's Changed

• [FIRRTL][Dedup] Improve diagnostic for failing to dedup due to public. by @dtzSiFive in #7426
• [Arc] Fix crash in the arc canonicalizer produced by the KeepOneVecOp optimization by @elhewaty in #7429
• [Arc] Make the canonicalizer shuffle the input vector elements before merging by @elhewaty in #7394
• [ImportVerilog] Add rvalue assignment pattern support by @fabianschuiki in #7428
• [OM] Add IntegerAttr -> Python int conversion by @seldridge in #7430
• [FIRRTL][LowerDPI] Lower FIRRTL vector to an open array type by @uenoku in #7305
• [Support] Add FVInt, a four-valued arbitrary precision integer by @fabianschuiki in #7422
• [Python][OM] Handle BoolAttr's before IntegerAttr's. by @dtzSiFive in #7438

Full Changelog: firtool-1.80.0...firtool-1.80.1

firtool-1.80.0

What's Changed

• [ESI Runtime] Port connect: add optional buffer size arg by @teqdruid in #7387
• [LLHD] Add TemporalCodeMotionPass by @maerhart in #7381
• [ImportVerilog] Support large integer constants by @fabianschuiki in #7391
• [ImportVerilog] Support for loop variables by @fabianschuiki in #7393
• [ImportVerilog] Support the power operator by @fabianschuiki in #7395
• [MooreToCore][NFC] Fix the visibility of hw.module. by @hailongSun2000 in #7396
• [FIRRTL] Touchup {parse,emit}-basic.fir for --parse-only. by @dtzSiFive in #7397
• [ESI Runtime] Distribute headers along with wheel by @teqdruid in #7400
• [Verif] Introduce Formal Contracts by @dobios in #7325
• [PrepareForEmission] Hoist registers in a procedural region with disallowLocalVariables by @uenoku in #7404
• [Moore] Clean up struct ops and add missing tests by @fabianschuiki in #7392
• [Scheduling] Replace macro use in problem definitions by @jopperm in #7320
• [FIRRTL] default layer specialization by @youngar in #7401
• [ImportVerilog] Support for String Types, String Literals by @wenhu1024 in #7403
• [ESI] MMIO: add read/write port to service by @teqdruid in #7407
• Support scf.if Op Lowering to Calyx by @jiahanxie353 in #6256
• [OM] Pass Python values back and forth, not Attributes. by @mikeurbach in #7417
• [docs] Remove confusing reset in Seq docs SV example by @TaoBi22 in #7419
• [FIRRTL][Dedup] Rework hashing for perf and bug fixes. by @dtzSiFive in #7420

New Contributors

• @wenhu1024 made their first contribution in #7403
• @jiahanxie353 made their first contribution in #6256

Full Changelog: firtool-1.79.0...firtool-1.80.0

firtool-1.79.0

What's Changed

• [ESI][Runtime] Publish Windows wheels by @teqdruid in #7363
• [firtool][test] Check layer specialization options work. by @dtzSiFive in #7364
• [SV][ExportVerilog] Add UnpackedOpenArrayType, cast op and emission by @uenoku in #7304
• [ImportVerilog] Add basic function support by @fabianschuiki in #7349
• [FIRRTL] Support layer-colored probes in force, force_initial. by @dtzSiFive in #7371
• [PrepareForEmission][Prettify] Extend allowExprInClock to handle new verif ops by @uenoku in #7332
• [FIRRTL] Add lowering support for inline layers by @rwy7 in #7322
• [CI] Report failure of clang-tidy by @rwy7 in #7355
• [ImportVerilog] Fix use after free by @fzi-hielscher in #7368
• [StringDebugInfoPred] Workaround FusedLoc bytecode issue by @uenoku in #7375
• [Seq] Fix ClockConstAttr definition to pass roundstrip test by @uenoku in #7379
• [ESI runtime] Host memory service by @teqdruid in #7367
• [CI][lit] Enable roundtrip tests in CI by @uenoku in #7377
• [ESI] Separate data delay from signaling standard by @teqdruid in #7354
• [Moore] Distinguish the dynamic and constant extract. by @hailongSun2000 in #7340
• [circt-bmc] Add LowerToBMC Pass by @TaoBi22 in #7343
• [FIRRTL][ProbesToSignals] Add pass to replace probes with signals. by @dtzSiFive in #7342

Full Changelog: firtool-1.78.1...firtool-1.79.0

What's Changed

• [ESI][Runtime] Publish Windows wheels by @teqdruid in #7363
• [firtool][test] Check layer specialization options work. by @dtzSiFive in #7364
• [SV][ExportVerilog] Add UnpackedOpenArrayType, cast op and emission by @uenoku in #7304
• [ImportVerilog] Add basic function support by @fabianschuiki in #7349
• [FIRRTL] Support layer-colored probes in force, force_initial. by @dtzSiFive in #7371
• [PrepareForEmission][Prettify] Extend allowExprInClock to handle new verif ops by @uenoku in #7332
• [FIRRTL] Add lowering support for inline layers by @rwy7 in #7322
• [CI] Report failure of clang-tidy by @rwy7 in #7355
• [ImportVerilog] Fix use after free by @fzi-hielscher in #7368
• [StringDebugInfoPred] Workaround FusedLoc bytecode issue by @uenoku in #7375
• [Seq] Fix ClockConstAttr definition to pass roundstrip test by @uenoku in #7379
• [ESI runtime] Host memory service by @teqdruid in #7367
• [CI][lit] Enable roundtrip tests in CI by @uenoku in #7377
• [ESI] Separate data delay from signaling standard by @teqdruid in #7354
• [Moore] Distinguish the dynamic and constant extract. by @hailongSun2000 in #7340
• [circt-bmc] Add LowerToBMC Pass by @TaoBi22 in #7343
• [FIRRTL][ProbesToSignals] Add pass to replace probes with signals. by @dtzSiFive in #7342

Full Changelog: firtool-1.78.1...firtool-1.79.0

firtool-1.78.1

What's Changed

• [ESI Runtime] If zlib not found, use FetchContent by @teqdruid in #7352
• [Seq] Canonicalize firreg with preset 0 by @prithayan in #7350
• [LLHD] Remove llhd-sim by @maerhart in #7351
• [LLHD] Use hw.inout instead of llhd.sig by @maerhart in #7353
• [LLHD] Replace entity with module by @maerhart in #6958
• [LLHD] Refactor llhd.proc and remove llhd.inst by @maerhart in #7357
• [Handshake] Fix library dependencies by @youngar in #7356
• [FIRRTL] LowerToHW: guard against folded operations by @youngar in #7358
• [firtool] Make layer specialization take a list of layers by @youngar in #7359

Full Changelog: firtool-1.78.0...firtool-1.78.1