[LLHD] Improve llhd-desequentialize pass

[AndreyVV-100]

Hi! I'm trying to erase llhd.process by using llhd-desequentialize pass in this code:

module Mod(input clk, input rstn, output logic b);
always @(posedge clk or negedge rstn)
begin
    if (!rstn)
        b <= 0;
    else
        b <= 1;
end
endmodule

But it thinks that there are 3 triggers and it couldn't be optimized. How can I support it? As I know, seq.compreg supports only one clock and one reset.

Btw, I found another misprint:

circt/lib/Dialect/LLHD/Transforms/DesequentializationPass.cpp

Line 655 in 6b4bea0

if (triggers[0].clocks.size() != 1 || triggers[0].clocks.size() != 1)

We should check triggers[0].kinds.size() != 1 instead of second condition.