[FIRRTL] LowerLayers RefSend could be Canonicalized Away

[seldridge]

The LowerLayers pass can create some trivial canonicalization opportunities. These can be removed with the canonicalizer. However, it may be better to handle these specially in the pass.

I specifically noticed that when you have a ref.resolve user of a captured value in a layerblock, this will create an input port and a ref.send. The ref.resolve(ref.send(block-arg)) can be trivially converted to block-arg. However, it doesn't fit a nice createOrFold pattern and would require special tracking. As I've been moving LowerLayers later and later, this has started to show up in small end-to-end firtool changes.

Consider:

firrtl.circuit "TestHarness" {
  firrtl.layer @Verification bind {
  }
  firrtl.module private @DUT(in %clock: !firrtl.clock, in %a: !firrtl.uint<32>, out %b: !firrtl.uint<32>, out %trace: !firrtl.probe<uint<32>, @Verification>) {
    %pc = firrtl.reg %clock : !firrtl.clock, !firrtl.uint<32>
    firrtl.matchingconnect %pc, %a : !firrtl.uint<32>
    firrtl.matchingconnect %b, %pc : !firrtl.uint<32>
    firrtl.layerblock @Verification {
      %x = firrtl.wire : !firrtl.probe<uint<32>, @Verification>
      %pc_d = firrtl.reg %clock : !firrtl.clock, !firrtl.uint<32>
      firrtl.matchingconnect %pc_d, %a : !firrtl.uint<32>
      %0 = firrtl.ref.send %pc_d : !firrtl.uint<32>
      %1 = firrtl.ref.cast %0 : (!firrtl.probe<uint<32>>) -> !firrtl.probe<uint<32>, @Verification>
      firrtl.ref.define %x, %1 : !firrtl.probe<uint<32>, @Verification>
      firrtl.ref.define %trace, %x : !firrtl.probe<uint<32>, @Verification>
    }
  }
  firrtl.module @TestHarness(in %clock: !firrtl.clock, in %reset: !firrtl.uint<1>, in %a: !firrtl.uint<32>, out %b: !firrtl.uint<32>) attributes {convention = #firrtl<convention scalarized>} {
    %dut_clock, %dut_a, %dut_b, %dut_trace = firrtl.instance dut @DUT(in clock: !firrtl.clock, in a: !firrtl.uint<32>, out b: !firrtl.uint<32>, out trace: !firrtl.probe<uint<32>, @Verification>)
    firrtl.matchingconnect %dut_clock, %clock : !firrtl.clock
    firrtl.matchingconnect %dut_a, %a : !firrtl.uint<32>
    firrtl.matchingconnect %b, %dut_b : !firrtl.uint<32>
    firrtl.layerblock @Verification {
      %0 = firrtl.ref.resolve %dut_trace : !firrtl.probe<uint<32>, @Verification>
      firrtl.printf %clock, %reset, "The last PC was: %x" (%0) : !firrtl.clock, !firrtl.uint<1>, !firrtl.uint<32>
    }
  }
}

This will be compiled to:

    firrtl.module private @TestHarness_Verification(in %dut_trace: !firrtl.uint<32>, in %clock: !firrtl.clock, in %reset: !firrtl.uint<1>) {
      %0 = firrtl.ref.send %dut_trace : !firrtl.uint<32>
      %1 = firrtl.ref.resolve %0 : !firrtl.probe<uint<32>>
      firrtl.printf %clock, %reset, "The last PC was: %x" (%1) : !firrtl.clock, !firrtl.uint<1>, !firrtl.uint<32>
    }